STAC9750XXTAEC1X IDT, Integrated Device Technology Inc, STAC9750XXTAEC1X Datasheet - Page 26

• Manufacturer Part Number: STAC9750XXTAEC1X
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of STAC9750XXTAEC1X

• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

IDT™
VALUE-LINE TWO-CHANNEL AC’97 CODECS
STAC9750/9751
VALUE-LINE TWO-CHANNEL AC’97 CODECS
Prior to any attempts at putting STAC9750/9751 into operation the AC'97 controller should poll the
first bit in the audio input frame (SDATA_IN slot 0, bit 15) for an indication that STAC9750/9751 has
become “CODEC Ready”. Once the STAC9750/9751 is sampled “CODEC Ready”, the next 12 bit
positions sampled by the AC'97 controller indicate which of the corresponding 12 time slots are
assigned to input data streams, and that they contain valid data. The following diagram illustrates the
time slot based AC-Link protocol.
A new audio input frame begins with a low to high transition of SYNC. SYNC is synchronous to the
rising edge of BIT_CLK. Immediately following the falling edge of BIT_CLK, the STAC9750/9751
samples the assertion of SYNC. This falling edge marks the time when both sides of AC-Link are
aware of the start of a new audio frame. On the next rising of BIT_CLK, the STAC9750/9751 transi-
tions SDATA_IN into the first bit position of slot 0 (“CODEC Ready” bit). Each new bit position is pre-
sented to AC-Link on a rising edge of BIT_CLK and subsequently sampled by the AC'97 controller
on the following falling edge of BIT_CLK. This sequence ensures that data transitions, and subse-
quent sample points for both incoming and outgoing data streams are time aligned.
SDATA_IN's composite stream is MSB justified (MSB first) with all non-valid bit positions (for
assigned and/or unassigned time slots) stuffed with 0s by STAC9750/9751. SDATA_IN data is sam-
pled on the falling edges of BIT_CLK.
5.1.2.1.
The status port is used to monitor status for STAC9750/9751 functions including, but not limited to,
mixer settings and power management.
SDATA_IN
BIT_CLK
End of previous audio frame
SYNC
Slot 1: Status Address Port
12.288 MHz
Figure 14. STAC9750/9751 Audio Input Frame
Frame
valid
Figure 15. Start of an Audio Input Frame
S D A T A _ IN
slot1
B IT _ C L K
E n d o f p r e v io u s a u d io f r a m e
Tag Phase
slot2
("1" = time slot contains valid PCM data)
S Y N C
Time Slot "Valid" Bits
slot(12)
"0"
26
"0"
a s s e r t e d
S Y N C
C o d e c
R e a d y
"0"
19
s lo t 1
S D A T A _ O U T
b it o f f r a m e
Slot 1
f ir s t
s lo t 2
"0"
19
Slot 2
20.8 uS (48 kHZ)
STAC9750/9751
Data Phase
"0"
19
Slot 3
"0"
19
PC AUDIO
Slot 12
V 5.8 103106
"0"