ADV7176AKS Analog Devices Inc, ADV7176AKS Datasheet - Page 31

• Manufacturer Part Number: ADV7176AKS
• Manufacturer: Analog Devices Inc

Specifications of ADV7176AKS

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Not Compliant

Time T
such that it appears T
the source that is gated by the TTXREQ signal in order to deliver TTX data.
With the programmability that is offered with TTXREQ signal on the Rising/Falling edges, the TTX data is always inserted at the
correct position of 10.2 µs after the leading edge of Horizontal Sync pulse, which enables a source interface with variable pipeline
delays.
The width of the TTXREQ signal must always be maintained so it allows the insertion of 360 (to comply with the Teletext Standard
“PAL–WST”) teletext bits at a text data rate of 6.9375 Mbits/s; this is achieved by setting TC03–TC00 to zero. The insertion
window is not open if the Teletext Enable bit (MR34) is set to zero.
Teletext Protocol
The relationship between the TTX bit clock (6.9375 MHz) and the system CLOCK (27 MHz) for 50 Hz is given as follows:
Thus 37 TTX bits correspond to 144 clocks (27 MHz) and each bit has a width of almost four clock cycles. The ADV7175A/ADV7176A
uses an internal sequencer and variable phase interpolation filter to minimize the phase jitter and thus generate a bandlimited signal
which can be outputted on the CVBS and Y outputs.
At the TTX input the bit duration scheme repeats after every 37 TTX bits or 144 clock cycles. The protocol requires that TTX bits
10, 19, 28, 37 are carried by three clock cycles, all other bits by four clock cycles. After 37 TTX bits, the next bits with three clock
cycles are 47, 56, 65 and 74. This scheme holds for all following cycles of 37 TTX bits, until all 360 TTX bits are completed. All
teletext lines are implemented in the same way. Individual control of teletext lines are controlled by Teletext Setup Registers.
PD
time needed by the ADV7175A/ADV7176A to interpolate input data on TTX and insert it onto the CVBS or Y outputs,
TTX
TTXREQ
CVBS/Y
t
t
TTX
HSYNC
SYNTTXOUT
PD
DATA
= PIPELINE DELAY THROUGH ADV7175A/ADV7176A
DEL
t
= TTXREQ TO TTX (PROGRAMMABLE RANGE = 4 BITS [0–15 CLOCK CYCLES])
PD
SYNTTXOUT
= 10.2 s
TELETEXT VBI LINE
= 10.2 µs after the leading edge of the horizontal signal. Time TTX
TTX
ST
10.2 s
t
SYNTTXOUT
TTX
DEL






TELETEXT INSERTION
27 MHz
6.9375 × 10
6.75 × 10
4
APPENDIX 3
t
RUN-IN CLOCK
PD
45 BYTES (360 BITS) – PAL

 = 6.75 MHz

6
PROGRAMMABLE PULSE EDGES
6

 = 1.027777

ADDRESS & DATA
ADV7175A/ADV7176A
DEL
is the pipeline delay time by