ADV7176AKS Analog Devices Inc, ADV7176AKS Datasheet - Page 10

• Manufacturer Part Number: ADV7176AKS
• Manufacturer: Analog Devices Inc

Specifications of ADV7176AKS

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Not Compliant

ADV7175A/ADV7176A
Pin
No.
1, 11, 20,
28, 30
10, 19, 21,
29, 43
15
16
17
18
22
23
24
25
26
27
31
32
33
34
35
36
37
38–42
2–9, 12–14
44
Mnemonic
V
GND
HSYNC
FIELD/VSYNC
BLANK
ALSB
RESET
SCLOCK
SDATA
COMP
DAC C
DAC D
DAC B
DAC A
V
R
SCRESET/RTC
TTXREQ/GND
TTX/V
P0–P15
CLOCK
AA
REF
SET
AA
Input/
Output
P
G
I/O
I/O
I/O
I
I
I
I/O
O
O
O
O
O
I/O
I
I
O
I
I
I
PIN FUNCTION DESCRIPTIONS
MPU Port Serial Data Input/Output.
This pin can be configured as an input by setting MR22 and MR21 of Mode
Teletext Data Request Signal/Defaults to GND when Teletext not selected
Function
Power Supply (3 V to 5 V).
Ground Pin.
HSYNC (Modes 1 and 2) Control Signal. This pin may be configured to
output (Master Mode) or accept (Slave Mode) Sync signals.
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. This
pin may be configured to output (Master Mode) or accept (Slave Mode)
these control signals.
Video Blanking Control Signal. The pixel inputs are ignored when this is
logic level “0.” This signal is optional.
TTL Address Input. This signal sets up the LSB of the MPU address.
The input resets the on chip timing generator and sets the ADV7175A/
ADV7176A into default mode. This is NTSC operation, Timing Slave Mode
0, 8-bit operation, 2 × composite and S-Video out and all DACs powered on.
MPU Port Serial Interface Clock Input.
Compensation Pin. Connect a 0.1 µF capacitor from COMP to V
Optimum Dynamic Performance in Low Power Mode, the value of the
COMP capacitor can be lowered to as low as 2.2 nF.
RED/S-Video C/V Analog Output.
GREEN/S-Video Y/Y Analog Output.
BLUE/Composite/U Analog Output.
PAL/NTSC Composite Video Output. Full-Scale Output is 180IRE (1286
mV) for NTSC and 1300 mV for PAL.
Voltage Reference Input for DACs or Voltage Reference Output (1.235 V).
A 150 Ω resistor connected from this pin to GND is used to control full-scale
amplitudes of the video signals.
Register 2. It can be configured as a subcarrier reset pin, in which case a low-
to-high transition on this pin will reset the subcarrier to Field 0. Alternatively
it may be configured as a Real Time Control (RTC) input.
(enables backward compatibility to ADV7175/ADV7176).
Teletext Data/Defaults to V
compatibility to ADV7175/ADV7176).
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or
16-Bit YCrCb Pixel Port (P0–P15). P0 represents the LSB.
TTL Clock Input. Requires a stable 27 MHz reference Clock for standard
operation. Alternatively, a 24.5454 MHz (NTSC) or 29.5 MHz (PAL) can be
used for square pixel operation.
AA
when Teletext not selected (enables backward
AA
. For