ADV7176AKS Analog Devices Inc, ADV7176AKS Datasheet - Page 25

• Manufacturer Part Number: ADV7176AKS
• Manufacturer: Analog Devices Inc

Specifications of ADV7176AKS

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: MQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Not Compliant

CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED0)
(Address [SR4–SR0] = 09–08H)
These 8-bit-wide registers are used to set up the closed captioning
extended data bytes on even fields. Figure 36 shows how the
high and low bytes are set up in the registers.
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD0)
(Subaddress [SR4–SR0] = 0B–0AH)
These 8-bit-wide registers are used to set up the closed captioning
data bytes on odd fields. Figure 37 shows how the high and low
bytes are set up in the registers.
TIMING REGISTER 1 (TR17–TR10)
(ADDRESS [SR4–SR0] = 0CH)
Timing Register 1 is an 8-Bit-Wide Register
Figure 38 shows the various operations under the control of
Timing Register 1. This register can be read from as well as
written to. This register can be used to adjust the width and
position of the master mode timing signals.
BYTE 0
BYTE 0
BYTE 1
BYTE 1
CED7
CCD7
CED15
CCD15
CED6
CCD6
CED14
CCD14
CED5
CCD5
TR17 TR16
CED13
CCD13
FIELD/VSYNC
TIMING MODE 1 (MASTER/PAL)
0
0
1
1
HSYNC TO PIXEL
DATA ADJUST
CED4
CCD4
HSYNC
0
1
0
1
CED12
CCD12
TR17
0 x T
1 x T
2 x T
3 x T
CED3
CCD3
CED11
CCD11
PCLK
PCLK
PCLK
PCLK
TR16
CED2
CCD2
T
LINE 1
B
T
CED10
CCD10
A
TR15 TR14
TR15 TR14
x
x
0
0
1
1
CED1
CCD1
RISING EDGE DELAY
HSYNC TO FIELD
(MODE 1 ONLY)
(MODE 2 ONLY)
VSYNC WIDTH
CED9
CCD9
TR15
0
1
0
1
0
1
CED0
CCD0
1 x T
4 x T
16 x T
128 x T
CED8
CCD8
T
T
B
B
T
+ 32 s
TR14
PCLK
PCLK
C
PCLK
PCLK
TR13 TR12
TR1 BIT DESCRIPTION
HSYNC Width (TR11–TR10)
These bits adjust the HSYNC pulsewidth.
HSYNC to FIELD/VSYNC Delay (TR13–TR12)
These bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
HSYNC to FIELD Rising Edge Delay (TR15–TR14)
When the ADV7175A/ADV7176A is in Timing Mode 1, these
bits adjust the position of the HSYNC output relative to the
FIELD output rising edge.
VSYNC Width (TR15–TR14)
When the ADV7175A/ADV7176A is in Timing Mode 2, these
bits adjust the VSYNC pulsewidth.
HSYNC to Pixel Data Adjust (TR17–TR16)
This enables the HSYNC to be adjusted with respect to the
pixel data. This allows the Cr and Cb components to be
swapped. This adjustment is available in both master and slave
timing modes.
MODE REGISTER 2 MR2 (MR27–MR20)
(Address [SR4–SR0] = 0DH)
Mode Register 2 is an 8-bit-wide register.
Figure 39 shows the various operations under the control of Mode
Register 2. This register can be read from as well as written to.
MR2 BIT DESCRIPTION
Square Pixel Control (MR20)
This bit is used to set up square pixel mode. This is available in
slave mode only. For NTSC, a 24.5454 MHz clock must be
supplied. For PAL, a 29.5 MHz clock must be supplied.
0
0
1
1
TR13
FIELD/VSYNC DELAY
HSYNC TO
0
1
0
1
TR12
0 x T
4 x T
8 x T
16 x T
T
T
PCLK
PCLK
PCLK
B
C
LINE 313
PCLK
TR11
TR11 TR10
0
0
1
1
HSYNC WIDTH
ADV7175A/ADV7176A
0
1
0
1
LINE 314
TR10
1 x T
4 x T
16 x T
128 x T
T
A
PCLK
PCLK
PCLK
PCLK