ADV7176AKS Analog Devices Inc, ADV7176AKS Datasheet - Page 19
ADV7176AKS
Manufacturer Part Number
ADV7176AKS
Description
Manufacturer
Analog Devices Inc
Datasheet
1.ADV7176AKS.pdf
(50 pages)
Specifications of ADV7176AKS
Adc/dac Resolution
10b
Screening Level
Commercial
Package Type
MQFP
Pin Count
44
Lead Free Status / RoHS Status
Not Compliant
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Mode 2: Master Option HSYNC, VSYNC, BLANK
(Timing Register 0 TR0 = X X X X X 1 0 1)
In this mode, the ADV7175A/ADV7176A can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an Odd Field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7175A/ADV7176A automatically blanks
all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 21 (NTSC) and Figure 22 (PAL). Figure 23 illus-
trates the HSYNC, BLANK and VSYNC for an even-to-odd field transition relative to the pixel data. Figure 24 illustrates the
HSYNC, BLANK and VSYNC for an odd-to-even field transition relative to the pixel data.
VSYNC
HSYNC
HSYNC
VSYNC
BLANK
BLANK
622
309
HSYNC
BLANK
VSYNC
PIXEL
DATA
HSYNC
BLANK
VSYNC
DISPLAY
DISPLAY
PIXEL
DATA
623
310
624
311
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
EVEN FIELD
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
ODD FIELD
625
312
313
1
314
2
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
315
3
ODD FIELD
VERTICAL BLANK
VERTICAL BLANK
EVEN FIELD
316
4
PAL = 132 * CLOCK/2
NTSC = 122 * CLOCK/2
PAL = 864 * CLOCK/2
NTSC = 858 * CLOCK/2
317
5
Cb
318
6
Y
319
7
Cr
Y
320
ADV7175A/ADV7176A
Cb
Cb
21
Y
334
22
Cr
DISPLAY
335
23
Y
DISPLAY
336