SAA7103HV4 NXP Semiconductors, SAA7103HV4 Datasheet - Page 76

• Manufacturer Part Number: SAA7103HV4
• Manufacturer: NXP Semiconductors

Specifications of SAA7103HV4

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: PQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
13. Test information
SAA7102_SAA7103_4
Product data sheet
13.1.1 Initialization of boundary scan circuit
13.1 Boundary scan test
Place the analog coupling (clamp) capacitors close to the analog input pins. Place the
analog termination resistors close to the coupling capacitors.
Be careful of hidden layout capacitors around the crystal application.
Use serial resistors in clock, sync and data lines, to avoid clock or data reflection effects
and to soften data energy.
The SAA7102; SAA7103 has built-in logic and 5 dedicated pins to support boundary scan
testing which allows board testing without special hardware (nails). The SAA7102;
SAA7103 follows the “IEEE Std. 1149.1 - Standard Test Access Port and Boundary-Scan
Architecture” set by the Joint Test Action Group (JTAG) chaired by Philips.
The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST),
Test Data Input (TDI) and Test Data Output (TDO).
The Boundary Scan Test (BST) functions BYPASS, EXTEST, SAMPLE, CLAMP and
IDCODE are all supported; see
found in the specification “IEEE Std. 1149.1”. A file containing the detailed Boundary Scan
Description Language (BSDL) of the SAA7102; SAA7103 is available on request.
Table 112: BST instructions supported by the SAA7102; SAA7103
The Test Access Port (TAP) controller of an IC should be in the reset state
(TEST_LOGIC_RESET) when the IC is in functional mode. This reset state also forces
the instruction register into a functional instruction such as IDCODE or BYPASS.
To solve the power-up reset, the standard specifies that the TAP controller will be forced
asynchronously to the TEST_LOGIC_RESET state by setting the TRST pin LOW.
Instruction
BYPASS
EXTEST
SAMPLE
CLAMP
IDCODE
Description
This mandatory instruction provides a minimum length serial path (1 bit)
between TDI and TDO when no test operation of the component is required.
This mandatory instruction allows testing of off-chip circuitry and board level
interconnections.
This mandatory instruction can be used to take a sample of the inputs during
normal operation of the component. It can also be used to preload data values
into the latched outputs of the boundary scan register.
This optional instruction is useful for testing when not all ICs have BST. This
instruction addresses the bypass register while the boundary scan register is
in external test mode.
This optional instruction will provide information on the components
manufacturer, part number and version number.
Rev. 04 — 18 January 2006
Table
112. Details about the JTAG BST-TEST can be
SAA7102; SAA7103
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
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