TDA8501T/N1,112 NXP Semiconductors, TDA8501T/N1,112 Datasheet - Page 11

• Manufacturer Part Number: TDA8501T/N1,112
• Manufacturer: NXP Semiconductors

Specifications of TDA8501T/N1,112

• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
Oscillator and Filter Control
The internal crystal oscillator is connected to pin 23 which
provides for the external connection of a crystal in series
with a trimmer to ground. It is possible to connect an
external signal source to pin 23, via a capacitor in series
with a resistor. The signal shape is not important.
Figure 11 shows the external components connected to
pin 23 and the required conditions. The minimum AC
current of 50 A must be determined by the resistors
(R
example, in this way an external sub-carrier, locked to the
sync, can be used.
The 3 dB of the low pass filters and the centre frequency
of the bandpass filter are controlled by the filter control
loop and directly coupled to the value of the frequency of
the oscillator. The external capacitor of the control loop is
connected to pin 15.
April 1993
PAL mode:
NTSC mode: frequency of the oscillator is
int
PAL/NTSC encoder
and R
Fig.11 Tuning circuit for external signal source.
ext
) and the voltage of the signal source. For
frequency of the oscillator is
4.433618 MHz.
3.579545 MHz.
11
Sync separator and Pulse shaper
The composite sync (CS) input at pin 24 (via the sync
separator) together with a sawtooth generator provide the
source for all pulses necessary for the processing.
Pulses are used for:
The value of the sawtooth generator output (current) is
determined by the value of a fixed resistor to ground which
is connected externally at pin 21 (BURST ADJ). When
finer tolerance of the burst position is required, the fixed
resistor is connected in series with a variable
potentiometer to ground. By use of the potentiometer the
burst position at the outputs can be finely adjusted, after
which the pulse width of the burst and the position and
pulse width of all other internal pulses are then
determined. When using a fixed resistor with a tolerance of
2%, a tolerance of 10% of the burst position can be
expected. Timing diagrams of the pulses are provided by
Figs 12 and 13.
H/2 at pin 4 is only necessary in the PAL mode when the
internal H/2 pulse requires locking with an external H/2
phase (two or more encoders locked in same phase). The
forcing of the internal H/2 to a desired phase is possible by
means of an external pulse. Forcing is active at HIGH
level.
For the functioning of Pin 4 in the NTSC mode see also
section Black and Blanking levels in PAL and NTSC
modes.
clamping
video blanking
H/2
chrominance blanking
burst pulse generation for adding to U, V
pulses for the modulator offset control.
Preliminary specification
TDA8501