TDA8501T/N1,112 NXP Semiconductors, TDA8501T/N1,112 Datasheet - Page 10

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TDA8501T/N1,112

Manufacturer Part Number
TDA8501T/N1,112
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of TDA8501T/N1,112

Lead Free Status / RoHS Status
Compliant
Philips Semiconductors
April 1993
PAL/NTSC encoder
Fig.10 Nominal Y +SYNC signal level at pin 22
Fig.9
(NTSC mode).
Nominal Y
(PAL mode).
SYNC signal level at pin 22
10
NTSC option with internal set-up generation
Pin 4 connected to ground or left open-circuit. The set-up
is generated internally and the input signals have the
values already specified in section Input stage. The set-up
is not suppressed during vertical sync.
NTSC option without internal set-up generation
Pin 4 connected to V
restrictions on the input signals as follows:
if the output signal must be according to the NTSC
standard, the input signals must be generated with a
specific set-up level
for R, G and B inputs a set-up level of 53 mV is required,
therefore the specified amplitude must be 753 mV
(peak-to-peak) instead of 700 mV (peak-to-peak)
for U, V and Y inputs a set-up level for Y of 76 mV is
required, therefore the specified amplitude must be
1076 mV (peak-to-peak) (without sync) instead of 1 V
(peak-to-peak). This option, combined with U, V and Y
inputs, is not possible if V
CC
. This option places some
CC
is
Preliminary specification
4.75 V.
TDA8501

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