STULPI01BTBR STMicroelectronics, STULPI01BTBR Datasheet - Page 37

• Manufacturer Part Number: STULPI01BTBR
• Manufacturer: STMicroelectronics

Specifications of STULPI01BTBR

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

STULPI01A - STULPI01B
Table 23.
Note:
Table 24.
Field name
Host disconnect
latch
VbusValid latch
SessValid latch
SessEnd latch
ID latch
Reserved
Register read data returned in
current clock cycle
USB interrupt latch register
Address 14h (Read-only with auto clear)
These bits are set by the STULPI01 when an unmasked change occurs on the
corresponding internal signal. The STULPI01 will automatically clear all bits when the link
reads this register, or when low power mode is entered. The STULPI01 also clears this
register when serial mode or car kit mode is entered regardless of the value of
ClockSuspendM. The interrupt circuitry is powered down in any mode when both rising and
falling edge enables are disabled. To ensure the interrupts are detectable when the clock is
powered down, the link should enable both rising and falling edges.
The STULPI01 follows the rules in
note that if the register read data is returned to the link in the same cycle that a USB
interrupt latch bit is to be set, the interrupt condition is given immediately in the register read
data and the latch bit is not set.
Note that it is optional for the link to read the USB interrupt latch register in synchronous
mode because the RX CMD byte already indicates the interrupt source directly.
Setting rules for interrupt latch register
Yes
Yes
No
No
Bits
7:5
0
1
2
3
4
Input conditions
Access
rd
rd
rd
rd
rd
rd
Interrupt latch bit is to be set in
current clock cycle
Reset
Doc ID 14817 Rev 3
0b
0b
0b
0b
0b
0b
Table 20
Yes
Yes
No
No
Set to 1b by the STULPI01 when an unmasked event
occurs on host disconnect. Cleared when this register is
read. Applicable only in host mode.
Set to 1b by the STULPI01 when an unmasked event
occurs on VbusValid. Cleared when this register is read.
Set to 1b by the STULPI01 when an unmasked event
occurs on SessValid. Cleared when this register is read.
SessValid is the same as UTMI+Avalid.
Set to 1b by the STULPI01 when an unmasked event
occurs on SessEnd. Cleared when this register is read.
Set to 1b by the STULPI01 when an unmasked event
occurs on ID. Cleared when this register is read. ID is valid
50ms after ID is set to 1b, otherwise ID is undefined and
should be ignored.
Reserved
for setting any latch register bit. It is important to
Resultant value of latch register bit
Description
0
1
0
0
ULPI registers
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