STULPI01BTBR STMicroelectronics, STULPI01BTBR Datasheet - Page 23

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STULPI01BTBR

Manufacturer Part Number
STULPI01BTBR
Description
Manufacturer
STMicroelectronics
Datasheet

Specifications of STULPI01BTBR

Number Of Transceivers
1
Esd Protection
YeskV
Operating Supply Voltage (typ)
Not RequiredV
Operating Temperature Classification
Industrial
Operating Supply Voltage (max)
Not RequiredV
Operating Supply Voltage (min)
Not RequiredV
Mounting
Surface Mount
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Lead Free Status / RoHS Status
Compliant

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0
STULPI01A - STULPI01B
Table 11.
Note:
6.16
6.17
6.18
6.18.1
6.18.2
Note:
linestate (0)
linestate (1)
reserved
Signal
INT
Low-power mode
Low-power mode is exited by asserting STP pin high. PLL is started immediately, and when
the clock becomes stable, it is passed on the output of CLK pin. Then after minimum of 5
clock cycles DIR is deasserted and low-power mode is exited. SuspendM bit is reset to 1b.
STP signal must be kept high until the DIR is deasserted, otherwise low-power mode will not
be exited.
Power-down mode
Power-down mode is entered by asserting the CSn/PWRDN pin high. Internal voltage
regulators are disabled, and the device has minimum possible power consumption.
STULPI01 has no wake-up capability or USB functionality during power down mode. This
mode can be exited by deasserting CSn/PWRDN pin. Voltage regulators will be turned on
and internal power-on-reset circuit will reset the chip to initial state. ULPI interface pins are
in high impedance state during power-down mode.
VIO OFF mode
In case
the device in VIO OFF mode is the same as in power-down mode.
Startup procedure
ULPI device detection
Link detects ULPI device presence by sampling the DIR signal at the reset time
The NXT signal is '0' after reset to signalize 8-bit device to link controller. CLK is '1' to
signalize a DDR capable device.
SDR mode selection
The STULPI01 samples the D0 line on the first rising edge of the output clock on the CLK
pin. When the sampled value is '0', the STULPI01 remains in SDR mode.
SDR mode can be selected again only after hardware reset. During software reset mode,
selection is not performed.
IMPORTANT: The controller must not drive the DATA lines to a value other than 0x00 or
0x01 during the first rising edge of ULPI CLK, otherwise the behavior of the device may be
undefined.
V
DVIO
Map to
is below the minimum value, the VIO OFF mode is entered. The behavior of
D0
D1
D2
D3
Doc ID 14817 Rev 3
Dir
out
out
out
out
Active high interrupt indication. Asserted whenever
Driven combinatorially from SE receivers
Driven combinatorially from SE receivers
any unmasked interrupt occurs.
Description
Reserved
Block description
(Figure
23/44
8).

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