ISP1504A1ETTM STEricsson, ISP1504A1ETTM Datasheet - Page 75

• Manufacturer Part Number: ISP1504A1ETTM
• Manufacturer: STEricsson

Specifications of ISP1504A1ETTM

• Lead Free Status / RoHS Status: Compliant

21. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. RXCMD A_VBUS_VLD indicator source . . . . . . .29
Fig 11. Example of register write, register read, extended
Fig 12. USB reset and high-speed detection handshake
Fig 13. Example of using the ISP1504x1 to transmit and
Fig 14. High-speed transmit-to-transmit packet timing . .36
Fig 15. High-speed receive-to-transmit packet timing . . .36
Fig 16. Preamble sequence . . . . . . . . . . . . . . . . . . . . . . .37
Fig 17. Full-speed suspend and resume . . . . . . . . . . . . .39
Fig 18. High-speed suspend and resume . . . . . . . . . . . .41
Fig 19. Remote wake-up from low-power mode . . . . . . .43
Fig 20. Transmitting USB packets without automatic SYNC
Fig 21. Example of transmit followed by receive in 6-pin
Fig 22. Example of transmit followed by receive in 3-pin
Fig 23. Rise time and fall time . . . . . . . . . . . . . . . . . . . . .65
Fig 24. Timing of TX_DAT and TX_SE0 to DP and DM. .65
Fig 25. Timing of TX_ENABLE to DP and DM. . . . . . . . .65
Fig 26. Timing of DP and DM to RX_RCV, RX_DP and
Fig 27. ULPI timing interface . . . . . . . . . . . . . . . . . . . . . .66
Fig 28. Bus turnaround timing . . . . . . . . . . . . . . . . . . . . .66
Fig 29. Using the ISP1504x1 with a standard USB
Fig 30. Using the ISP1504x1 with an OTG Controller;
Fig 31. Using the ISP1504x1 with a standard USB Host
Fig 32. Package outline SOT912-1 (TFBGA36) . . . . . . .71
CD00222688
Product data sheet
ULPI bus is ready for use . . . . . . . . . . . . . . . . . .23
CS_N/PWRDN. . . . . . . . . . . . . . . . . . . . . . . . . . .25
ISP1504x1 to the link. . . . . . . . . . . . . . . . . . . . . .27
register write and extended register read . . . . . .31
(chirp) sequence . . . . . . . . . . . . . . . . . . . . . . . . .33
receive USB data . . . . . . . . . . . . . . . . . . . . . . . . .34
and EOP generation . . . . . . . . . . . . . . . . . . . . . .44
serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
RX_DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Peripheral Controller; external crystal . . . . . . . . .68
external 5 V source with built-in FAULT and external
square wave input on pin XTAL1 . . . . . . . . . . . . .69
Controller; external 5 V source with built-in FAULT
and external crystal . . . . . . . . . . . . . . . . . . . . . . .70
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin configuration TFBGA36; top view . . . . . . . . . .5
Application circuit components . . . . . . . . . . . . . .12
Entering and exiting 3-state in normal mode . . . .18
Internal power-on reset timing . . . . . . . . . . . . . . .21
Power-up and reset sequence required before the
Interface behavior with respect to RESET_N . . .24
Interface behavior with respect to
Single and back-to-back RXCMDs from the
Rev. 04 — 20 May 2010
ISP1504A1; ISP1504C1
ULPI HS USB OTG transceiver
© ST-ERICSSON 2010. All rights reserved.
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