ISP1504A1ETTM STEricsson, ISP1504A1ETTM Datasheet - Page 74

• Manufacturer Part Number: ISP1504A1ETTM
• Manufacturer: STEricsson

Specifications of ISP1504A1ETTM

• Lead Free Status / RoHS Status: Compliant

20. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. TXCMD byte format . . . . . . . . . . . . . . . . . . . . .26
Table 11. RXCMD byte format . . . . . . . . . . . . . . . . . . . .27
Table 12. LINESTATE[1:0] encoding for upstream facing
Table 13. LINESTATE[1:0] encoding for downstream facing
Table 14. Encoded V
Table 15. V
Table 16. Encoded USB event signals . . . . . . . . . . . . . .30
Table 17. PHY pipeline delays . . . . . . . . . . . . . . . . . . . .34
Table 18. Link decision times . . . . . . . . . . . . . . . . . . . . .35
Table 19. Immediate register set overview . . . . . . . . . . .48
Table 20. Extended register set overview . . . . . . . . . . . .48
Table 21. Vendor ID Low register (address R = 00h) bit
Table 22. Vendor ID High register (address R = 01h) bit
Table 23. Product ID Low register (address R = 02h) bit
Table 24. Product ID High register (address R = 03h) bit
Table 25. Function Control register (address R = 04h to 06h,
Table 26. Function Control register (address R = 04h to 06h,
Table 27. Interface Control register (address R = 07h to 09h,
Table 28. Interface Control register (address R = 07h to 09h,
Table 29. OTG Control register (address R = 0Ah to 0Ch,
Table 30. OTG Control register (address R = 0Ah to 0Ch,
Table 31. USB Interrupt Enable Rising Edge register
Table 32. USB Interrupt Enable Rising Edge register
Table 33. USB Interrupt Enable Falling Edge register
Table 34. USB Interrupt Enable Falling Edge register
CD00222688
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended V
ULPI signal description . . . . . . . . . . . . . . . . . .14
Signal mapping during low-power mode . . . . .16
Signal mapping for 6-pin serial mode . . . . . . .16
Signal mapping for 3-pin serial mode . . . . . . .17
Operating states and corresponding resistor
settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
OTG Control register power control bits . . . . .25
ports: peripheral . . . . . . . . . . . . . . . . . . . . . . . .27
ports: host . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
applications . . . . . . . . . . . . . . . . . . . . . . . . . . .29
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
W = 04h, S = 05h, C = 06h) bit allocation . . . .49
W = 04h, S = 05h, C = 06h) bit description . . .50
W = 07h, S = 08h, C = 09h) bit allocation . . . .50
W = 07h, S = 08h, C = 09h) bit description . . .51
W = 0Ah, S = 0Bh, C = 0Ch) bit allocation . . .51
W = 0Ah, S = 0Bh, C = 0Ch) bit description . .52
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C =
0Fh) bit allocation . . . . . . . . . . . . . . . . . . . . . .52
(address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C =
0Fh) bit description . . . . . . . . . . . . . . . . . . . . .53
(address R = 10h to 12h, W = 10h, S = 11h, C =
12h) bit allocation . . . . . . . . . . . . . . . . . . . . . .53
(address R = 10h to 12h, W = 10h, S = 11h, C =
12h) bit description . . . . . . . . . . . . . . . . . . . . .53
BUS
indicators in RXCMD required for typical
BUS
voltage state . . . . . . . . . . . . . .28
BUS
capacitor value . . . . . . .12
Rev. 04 — 20 May 2010
Table 35. USB Interrupt Status register (address R = 13h)
Table 36. USB Interrupt Status register (address R = 13h)
Table 37. USB Interrupt Latch register (address R = 14h) bit
Table 38. USB Interrupt Latch register (address R = 14h) bit
Table 39. Debug register (address R = 15h) bit
Table 40. Debug register (address R = 15h) bit
Table 41. Scratch register (address R = 16h to 18h, W =
Table 42. Power Control register (address R = 3Dh to 3Fh,
Table 43. Power Control register (address R = 3Dh to 3Fh,
Table 44. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 45. Recommended operating conditions . . . . . . . 57
Table 46. Static characteristics: supply pins . . . . . . . . . . 58
Table 47. Static characteristics: digital pins CLOCK, DIR,
Table 48. Static characteristics: digital pin FAULT . . . . . 59
Table 49. Static characteristics: digital pin PSW_N . . . . 59
Table 50. Static characteristics: analog I/O pins DP, DM 59
Table 51. Static characteristics: analog pin V
Table 52. Static characteristics: ID detection circuit . . . . 61
Table 53. Static characteristics: resistor reference . . . . . 61
Table 54. Dynamic characteristics: reset and clock . . . . 62
Table 55. Dynamic characteristics: digital I/O pins . . . . . 63
Table 56. Dynamic characteristics: other characteristics 63
Table 57. Dynamic characteristics: analog I/O pins DP and
Table 58. Recommended list of materials . . . . . . . . . . . . 67
Table 59. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 60. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 73
ISP1504A1; ISP1504C1
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 54
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 54
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
16h, S = 17h, C = 18h) bit description . . . . . . 55
W = 3Dh, S = 3Eh, C = 3Fh) bit allocation . . . 55
W = 3Dh, S = 3Eh, C = 3Fh) bit description . . 56
STP, NXT, DATA[7:0], RESET_N, CS_N/PWRDN
58
DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
ULPI HS USB OTG transceiver
© ST-ERICSSON 2010. All rights reserved.
BUS
. . . . . . 61
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