ISP1504A1ETTM STEricsson, ISP1504A1ETTM Datasheet - Page 51

• Manufacturer Part Number: ISP1504A1ETTM
• Manufacturer: STEricsson

Specifications of ISP1504A1ETTM

• Lead Free Status / RoHS Status: Compliant

Table 28.
Table 29.
CD00222688
Product data sheet
Bit
7
6
5
4
3
2
1
0
Bit
Symbol
Reset
Access
Symbol
INTF_PROT_DIS
IND_PASSTHRU
IND_COMPL
-
CLOCK_
SUSPENDM
-
3PIN_FSLS_
SERIAL
6PIN_FSLS_
SERIAL
Interface Control register (address R = 07h to 09h, W = 07h, S = 08h, C = 09h) bit description
OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit allocation
USE_EXT_
VBUS_IND
10.1.4 OTG Control register
R/W/S/C
7
0
This register controls various OTG functions of the ISP1504x1. The bit allocation of the
OTG Control register is given in
VBUS_EXT
Description
Interface Protect Disable: Controls circuitry built into the ISP1504x1 to protect the ULPI
interface when the link 3-states STP and DATA[7:0]. When this bit is enabled, the ISP1504x1
will automatically detect when the link stops driving STP.
0b — Enables the interface protect circuit (default). The ISP1504x1 attaches a weak pull-up
resistor on STP. If STP is unexpectedly HIGH, the ISP1504x1 attaches weak pull-down
resistors on DATA[7:0], protecting data inputs.
1b — Disables the interface protect circuit, detaches weak pull-down resistors on DATA[7:0],
and a weak pull-up resistor on STP.
Indicator Pass-through: Controls whether the complement output is qualified with the internal
A_VBUS_VLD comparator before being used in the V
Section
0b — The complement output signal is qualified with the internal A_VBUS_VLD comparator
(default).
1b — The complement output signal is not qualified with the internal A_VBUS_VLD
comparator.
Indicator Complement: Informs the PHY to invert the FAULT input signal, generating the
complement output. For details, see
0b — The ISP1504x1 will not invert the FAULT signal (default).
1b — The ISP1504x1 will invert the FAULT signal.
reserved
Clock Suspend LOW: Active LOW clock suspend.
Powers down the internal clock circuitry only. By default, the clock will not be powered in 6-pin
serial mode or 3-pin serial mode.
Valid only in 6-pin serial mode and 3-pin serial mode. Valid only when SUSPENDM is set to
logic 1, otherwise this bit is ignored.
0b — Clock will not be powered in 3-pin or 6-pin serial mode.
1b — Clock will be powered in 3-pin and 6-pin serial modes.
reserved
3-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 3-bit serial
interface. The PHY will automatically clear this bit when 3-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface.
1b — Full-speed or low-speed packets are sent using the 3-pin serial interface.
6-Pin Full-Speed Low-Speed Serial Mode: Changes the ULPI interface to a 6-bit serial
interface. The PHY will automatically clear this bit when 6-pin serial mode is exited.
0b — Full-speed or low-speed packets are sent using the parallel interface.
1b — Full-speed or low-speed packets are sent using the 6-pin serial interface.
R/W/S/C
DRV_
6
0
9.5.2.2.
reserved
R/W/S/C
5
0
Rev. 04 — 20 May 2010
R/W/S/C
CHRG_
VBUS
Table
4
0
Section
29.
DISCHRG_
ISP1504A1; ISP1504C1
R/W/S/C
VBUS
9.5.2.2.
3
0
BUS
DM_PULL
R/W/S/C
DOWN
state in RXCMD. For details, see
ULPI HS USB OTG transceiver
2
1
DP_PULL
R/W/S/C
DOWN
© ST-ERICSSON 2010. All rights reserved.
1
1
ID_PULL
R/W/S/C
UP
0
0
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