XR88C681CP/40 Exar Corporation, XR88C681CP/40 Datasheet - Page 50

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XR88C681CP/40

Manufacturer Part Number
XR88C681CP/40
Description
Dual Channel UART
Manufacturer
Exar Corporation
Datasheet

Specifications of XR88C681CP/40

Features
*
Number Of Channels
2, DUART
Fifo's
1 Byte, 3 Byte
Voltage - Supply
5V
With Parallel Port
Yes
With Cmos
Yes
Mounting Type
Through Hole
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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D. TIMING CONTROL BLOCK
The Timing Control Block allows to the user to specify the
bit rates that he/she wishes to transmit and receive data at
each channel. The Timing Control Block consists of the
following elements:
D Oscillator Circuit
D Bit Rate Generator
V
cc
Rev. 2.11
MN/
HOLD
-
DT/
DEN
8086 CPU
-
-
R
MX
AD8 - AD15
AD0 - AD7
Figure 23. Schematic of the XR88C681 DUART Device Interfacing to a
M/
-
INTR
INTA
ALE
-
-
RD
WR
-
IO
“Min” Mode 8086 CPU Device
D
C
D
C
74LS373
74LS373
D0 - D7
Q
Q
D8 - D15
50
A8 - A15
D 16 bit Counter/Timer
D 4 - External Input Pins (to clock the Transmitters
D Two Clock Select Registers (32:1 MUXs)
Figure 24 presents a block diagram of the Timing Control
block for the XR88C681 device.
and Receivers, directly)
A4 - A7
-
MEMW
-
MEMR
from higher
priority device
Address
Decoder
A0 - A3
A0 - A3
-
-
-
-
-
IEI
D0 - D7
IACK
RD
WR
CS
INTR
XR88C681

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