XR88C681CP/40 Exar Corporation, XR88C681CP/40 Datasheet - Page 16

• Manufacturer Part Number: XR88C681CP/40
• Description: Dual Channel UART
• Manufacturer: Exar Corporation

Specifications of XR88C681CP/40

• Features: *
• Number Of Channels: 2, DUART
• Fifo's: 1 Byte, 3 Byte
• Voltage - Supply: 5V
• With Parallel Port: Yes
• With Cmos: Yes
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

appropriate data to the appropriate channel’s Command Register. Therefore, both Mode Registers, within a given
channel, have the same logical address. The features and functions of the DUART that are controlled by the Mode
Registers are discussed in detail in Section G.3.
B.2 Command Decoding
Each channel is equipped with a Command Register. In general, the role of these Command Registers are to
enable/disable the Transmitter, enable/disable the Receiver, along with facilitating a series of other miscellaneous
commands. The bit format for each Command Register is presented herewith.
The function of the lower nibble of the Command Registers is fairly straight-forward. This nibble is used to either enable
or disable the Transmitter and/or Receiver.
The upper nibble of the Command Register is used to invoke a series of miscellaneous commands. Table 3 defines the
commands associated with the upper nibble of the Command Registers. Please note that the upper nibble commands
1
effects system (or chip) level operation.
16
through B
Rev. 2.11
Bit 7
Bit 7
0
0
0
0
16
Miscellaneous Commands
effects only the performance of Command Register’s Channel. However, commands C
Table 3. Miscellaneous Commands, Upper Nibble of all Command Registers,
Table 2. (CRA, CRB) Bit Format for Command Registers of Channels A & B
Bit 6
See Following Text
Bit 6
0
0
0
0
Unless Otherwise Specified (Cont’d Next Page)
Bit 5
Bit 5
0
0
1
1
Bit 4
Bit 4
16
0
1
0
1
11 = Not valid (do not use)
Bit 3
Enable/Disable
00 = No Change
01 = Enable Rx
10 = Disable Rx
Description
Null Command.
Reset MRn Pointer. Causes the Channel’s MRn
pointer to point to MR1n.
Reset Receiver. Reset the individual channel re-
ceiver as if a Hardware Reset has been applied.
The Receiver is disabled and the FIFO is flushed.
Reset Transmitter. Resets the individual channel
transmitter as if a Hardware Reset had been applied.
The TXDn output is forced to a high level.
Receiver
Bit 2
11 = Not Valid (Do not use)
Bit 1
Enable/Disable
00 = No Change
10 = Disable Tx
01 = Enable Tx
Transmitter
16
Bit 0
and D
16