PIC24FJ64GA110-I/PT Microchip Technology, PIC24FJ64GA110-I/PT Datasheet - Page 202

• Manufacturer Part Number: PIC24FJ64GA110-I/PT
• Description: 16-bit, 16 MIPS, 64KB Flash, 16Kb RAM, 84 I/O, NanoWatt 100 TQFP 12x12x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ64GA110-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 64KB (22K x 24)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP
• Processor Series: PIC24FJ256GA110
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: UART, I2C, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Timers: 5
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC24FJ256GA110 FAMILY
REGISTER 18-1:
DS39905E-page 202
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12-11
bit 10
bit 9
bit 8
bit 7-6
bit 5
bit 4
bit 3
Note 1:
PMPEN
R/W-0
R/W-0
CSF1
These bits have no effect when their corresponding pins are used as address lines.
PMPEN: Parallel Master Port Enable bit
1 = PMP enabled
0 = PMP disabled, no off-chip access performed
Unimplemented: Read as ‘0’
PSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = Reserved
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on
00 = Address and data appear on separate pins
PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode)
1 = PMBE port enabled
0 = PMBE port disabled
PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port enabled
0 = PMWR/PMENB port disabled
PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port enabled
0 = PMRD/PMWR port disabled
CSF<1:0>: Chip Select Function bits
11 = Reserved
10 = PMCS1 and PMCS2 function as chip select
01 = PMCS2 functions as chip select, PMCS1 functions as address bit 14
00 = PMCS1 and PMCS2 function as address bits 15 and 14
ALP: Address Latch Polarity bit
1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
CS2P: Chip Select 2 Polarity bit
1 = Active-high (PMCS2/PMCS2)
0 = Active-low (PMCS2/PMCS2)
CS1P: Chip Select 1 Polarity bit
1 = Active-high (PMCS1/PMCS1)
0 = Active-low (PMCS1/PMCS1)
R/W-0
CSF0
U-0
—
PMA<10:8>
PMCON: PARALLEL MASTER PORT CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
R/W-0
R/W-0
PSIDL
ALP
(1)
ADRMUX1
(1)
R/W-0
(1)
(1)
R/W-0
CS2P
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ADRMUX0
R/W-0
R/W-0
CS1P
(1)
PTBEEN
R/W-0
R/W-0
BEP
 2010 Microchip Technology Inc.
x = Bit is unknown
PTWREN
WRSP
R/W-0
R/W-0
PTRDEN
R/W-0
R/W-0
RDSP
bit 8
bit 0