PIC24FJ32GA104-I/PT Microchip Technology, PIC24FJ32GA104-I/PT Datasheet - Page 60

• Manufacturer Part Number: PIC24FJ32GA104-I/PT
• Description: 16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GA104-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24FJ64GA104 FAMILY
REGISTER 6-1:
DS39951C-page 60
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13-11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
Note 1:
TRAPR
R/W-0
R/W-0
EXTR
2:
All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address
0 = An illegal opcode or uninitialized W Reset has not occurred
Unimplemented: Read as ‘0’
DPSLP: Deep Sleep Mode Flag bit
1 = Deep Sleep has occurred
0 = Deep Sleep has not occurred
CM: Configuration Word Mismatch Reset Flag bit
1 = A Configuration Word Mismatch Reset has occurred
0 = A Configuration Word Mismatch Reset has not occurred
PMSLP: Program Memory Power During Sleep bit
1 = Program memory bias voltage remains powered during Sleep
0 = Program memory bias voltage is powered down during Sleep and voltage regulator enters Standby mode
EXTR: External Reset (MCLR) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1 = A RESET instruction has been executed
0 = A RESET instruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit
1 = WDT is enabled
0 = WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
SLEEP: Wake From Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
IDLE: Wake-up From Idle Flag bit
1 = Device has been in Idle mode
0 = Device has not been in Idle mode
IOPUWR
R/W-0
R/W-0
SWR
Pointer caused a Reset
RCON: RESET CONTROL REGISTER
CO = Clearable Only bit
W = Writable bit
‘1’ = Bit is set
SWDTEN
R/W-0
U-0
—
(2)
WDTO
R/W-0
U-0
—
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
(2)
SLEEP
R/W-0,
U-0
—
(1)
R/CO-0, HS
DPSLP
R/W-0
IDLE
 2010 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-1
BOR
CM
PMSLP
R/W-0
R/W-1
POR
bit 8
bit 0