PIC24FJ32GA104-I/PT Microchip Technology, PIC24FJ32GA104-I/PT Datasheet - Page 214

• Manufacturer Part Number: PIC24FJ32GA104-I/PT
• Description: 16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GA104-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Note that the appropriate positions are set to ‘1’ to indi-
PIC24FJ64GA104 FAMILY
20.1
20.1.1
The CRC module can be programmed for CRC
polynomials of up to the 32nd order, using up to 32 bits.
Polynomial length, which reflects the highest exponent
in the equation, is selected by the PLEN<4:0> bits
(CRCCON2<4:0>).
The CRCXORL and CRCXORH registers control which
exponent terms are included in the equation. Setting a
particular bit includes that exponent term in the
equation; functionally, this includes an XOR operation
on the corresponding bit in the CRC engine. Clearing
the bit disables the XOR.
For example, consider two CRC polynomials, one a
16-bit equation and the other, a 32-bit equation:
To program these polynomials into the CRC generator,
set the register bits as shown in Table 20-1.
cate that they are used in the equation (for example, X26
and X23). The 0 bit required by the equation is always
XORed; thus, X0 is a don’t care. For a polynomial of
length N, it is assumed that the Nth bit will always be
used, regardless of the bit setting. Therefore, for a poly-
nomial length of 32, there is no 32nd bit in the CRCxOR
register.
20.1.2
The module incorporates a FIFO that works with a vari-
able data width. Input data width can be configured to
any value between one and 32 bits using the
DWIDTH<4:0> bits (CRCCON2<12:8>). When the
data width is greater than 15, the FIFO is four words
deep. When the DWIDTH value is between 15 and 8,
the FIFO is 8 words deep. When the DWIDTH value is
less than 8, the FIFO is 16 words deep.
TABLE 20-1:
DS39951C-page 214
x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7
PLEN<4:0>
X<31:16>
X<15:0>
CRC Control
Bits
User Interface
POLYNOMIAL INTERFACE
DATA INTERFACE
+ x5 + x4 + x2 + x + 1
x16 + x12 + x5 + 1
CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIAL
and
0000 0000 0000 000x
0001 0000 0010 000x
16-Bit Polynomial
01111
Bit Values
The data for which the CRC is to be calculated must
first be written into the FIFO. Even if the data width is
less than 8, the smallest data element that can be writ-
ten into the FIFO is one byte. For example, if the
DWIDTH value is five, then the size of the data is
DWIDTH + 1, or six. The data is written as a whole byte;
the two unused upper bits are ignored by the module.
Once data is written into the MSb of the CRCDAT reg-
isters (that is, MSb as defined by the data width), the
value of the VWORD<4:0> bits (CRCCON1<12:8>)
increments by one. For example, if the DWIDTH value
is 24, the VWORD bits will increment when bit 7 of
CRCDATH is written. Therefore, CRCDATL must
always be written before CRCDATH.
The CRC engine starts shifting data when the CRCGO
bit is set and the value of VWORD is greater than zero.
Each word is copied out of the FIFO into a buffer
register, which decrements VWORD. The data is then
shifted out of the buffer. The CRC engine continues
shifting at a rate of two bits per instruction cycle, until
the VWORD value reaches zero. This means that for a
given data width, it takes half that number of instruc-
tions for each word to complete the calculation. For
example, it takes 16 cycles to calculate the CRC for a
single word of 32-bit data.
When the VWORD value reaches the maximum value
for the configured value of DWIDTH (4, 8 or 16), the
CRCFUL bit becomes set. When the VWORD value
reaches zero, the CRCMPT bit becomes set. The FIFO
is emptied and the VWORD<4:0> bits are set to
‘00000’ whenever CRCEN is ‘0’.
At least one instruction cycle must pass, after a write to
CRCDAT, before a read of the VWORD bits is done.
0000 0100 1100 0001
0001 1101 1011 011x
32-Bit Polynomial
 2010 Microchip Technology Inc.
11111