PIC24FJ32GA104-I/PT Microchip Technology, PIC24FJ32GA104-I/PT Datasheet - Page 117
PIC24FJ32GA104-I/PT
Manufacturer Part Number
PIC24FJ32GA104-I/PT
Description
16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 44 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® XLP™ 24Fr
Datasheets
1.PIC24FJ32GA102-ISP.pdf
(308 pages)
2.PIC24FJ32GA102-ISP.pdf
(12 pages)
3.PIC24FJ32GA102-ISP.pdf
(48 pages)
Specifications of PIC24FJ32GA104-I/PT
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
32KB (11K x 24)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 13x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
876-1004 - PIC24 BREAKOUT BOARD
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
PIC24FJ32GA104-I/PT
Manufacturer:
Microchip
Quantity:
567
Company:
Part Number:
PIC24FJ32GA104-I/PT
Manufacturer:
Microchip Technology
Quantity:
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Part Number:
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Manufacturer:
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Quantity:
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- PIC24FJ32GA102-ISP PDF datasheet
- PIC24FJ32GA102-ISP PDF datasheet #2
- PIC24FJ32GA102-ISP PDF datasheet #3
- Current page: 117 of 308
- Download datasheet (3Mb)
REGISTER 9-1:
2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
bit 15
bit 14-2
bit 1
bit 0
Note 1:
R/W-0, HC
DSEN
U-0
—
2:
3:
(1)
These bits are reset only in the case of a POR event outside of Deep Sleep mode.
Reset value is ‘0’ for initial power-on POR only and ‘1’ for Deep Sleep POR.
This is a status bit only; a DSBOR event will NOT cause a wake-up from Deep Sleep.
DSEN: Deep Sleep Enable bit
1 = Device enters Deep Sleep when PWRSAV #0 is executed in the next instruction
0 = Device enters normal Sleep when PWRSAV #0 is executed
Unimplemented: Read as ‘0’
DSBOR: Deep Sleep BOR Event Status bit
1 = The DSBOR was active and a BOR event was detected during Deep Sleep
0 = The DSBOR was disabled or was active and did not detect a BOR event during Deep Sleep
RELEASE: I/O Pin State Deep Sleep Release bit
1 = I/O pins and SOSC maintain their states following exit from Deep Sleep, regardless of their LAT
0 = I/O pins and SOSC are released from their Deep Sleep states. The pin state is controlled by the
and TRIS configuration
LAT and TRIS configurations, and the SOSCEN bit.
U-0
U-0
—
—
DSCON: DEEP SLEEP CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
HS = Hardware Settable bit
U-0
U-0
—
—
(1)
PIC24FJ64GA104 FAMILY
U-0
U-0
—
—
(1,2,3)
C = Clearable bit
‘0’ = Bit is cleared
HCS = Hardware Clearable/Settable bit
U-0
U-0
—
—
(1,2)
U-0
U-0
—
—
U = Unimplemented, read as ‘0’
x = Bit is unknown
R/W-0, HCS
DSBOR
U-0
—
(1,2,3)
DS39951C-page 117
RELEASE
R/C-0, HS
U-0
—
(1,2)
bit 8
bit 0
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