PIC24FJ32GA104-I/PT Microchip Technology, PIC24FJ32GA104-I/PT Datasheet - Page 239

• Manufacturer Part Number: PIC24FJ32GA104-I/PT
• Description: 16-bit, 16 MIPS, 32KB Flash, 8KB RAM, Nanowatt XLP 44 TQFP 10x10x1mm TRAY
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ32GA104-I/PT

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 32KB (11K x 24)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

25.0
PIC24FJ64GA104 family devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming
• In-Circuit Emulation
25.1
The Configuration bits can be programmed (read as ‘0’),
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped starting at
program memory location F80000h. A detailed explana-
tion of the various bit functions is provided in
Register 25-1 through Register 25-6.
Note that address F80000h is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (800000h-FFFFFFh) which can only be
accessed using table reads and table writes.
TABLE 25-1:
 2010 Microchip Technology Inc.
Note:
PIC24FJ32GA10x
PIC24FJ64GA10x
SPECIAL FEATURES
Configuration Bits
Device
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information, refer to the
following sections of the “PIC24F Family
Reference Manual”:
• Section 9. “Watchdog Timer (WDT)”
• Section 32. “High-Level Device
• Section 33. “Programming and
(DS39697)
Integration” (DS39719)
Diagnostics” (DS39716)
FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ64GA104 FAMILY
DEVICES
ABFEh
57FEh
1
PIC24FJ64GA104 FAMILY
Configuration Word Addresses
ABFCh
57FCh
2
25.1.1
In PIC24FJ64GA104 family devices, the configuration
bytes are implemented as volatile memory. This means
that configuration data must be programmed each time
the device is powered up. Configuration data is stored in
the three words at the top of the on-chip program mem-
ory space, known as the Flash Configuration Words.
Their specific locations are shown in Table 25-1. These
are packed representations of the actual device Config-
uration bits, whose actual locations are distributed
among several locations in configuration space. The
configuration data is automatically loaded from the Flash
Configuration Words to the proper Configuration
registers during device Resets.
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Word for configuration data. This is
to make certain that program code is not stored in this
address when the code is compiled.
The upper byte of all Flash Configuration Words in pro-
gram memory should always be ‘1111 1111’. This
makes them appear to be NOP instructions in the
remote event that their locations are ever executed by
accident. Since Configuration bits are not implemented
in the corresponding locations, writing ‘1’s to these
locations has no effect on device operation.
Note:
Note:
operations on the last page of program
CONSIDERATIONS FOR
CONFIGURING PIC24FJ64GA104
FAMILY DEVICES
Configuration data is reloaded on all types
of device Resets.
Performing a page erase operation on the
last page of program memory clears the
Flash Configuration Words, enabling code
protection as a result. Therefore, users
should avoid performing page erase
memory.
ABFAh
57FAh
3
DS39951C-page 239
ABF8h
57F8h
4