PIC24F04KA200T-I/ST Microchip Technology, PIC24F04KA200T-I/ST Datasheet - Page 8

• Manufacturer Part Number: PIC24F04KA200T-I/ST
• Description: PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F04KA200T-I/ST

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (1.375K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

program.
PIC24FXXKA2XX
3.4
3.4.1
The NVMCON register controls the Flash memory write
and erase operations. To program the device, set the
NVMCON register to select the type of erase operation
(see
the WR control bit (NVMCON<15>) to initiate the
In ICSP mode, all programming operations are
self-timed. There is an internal delay between setting and
automatic clearing of the WR control bit when the
programming
Section 5.0 “AC/DC Characteristics and Timing
Requirements”
with various programming operations.
3.4.2
The WR bit (NVMCON<15>) is used to start an erase
or write cycle. Initiate the programming cycle by setting
the WR bit.
All erase and write cycles are self-timed. The WR bit
should be polled to determine if the erase or write cycle
is completed. Start a programming cycle as follows:
DS39991A-page 8
BSET
Table
Flash Memory Programming in
ICSP Mode
3-2) or write operation (see
PROGRAMMING OPERATIONS
STARTING AND STOPPING A
PROGRAMMING CYCLE
NVMCON, #WR
operation
for information on the delays associated
is
complete.
Table
Refer
3-3). Set
to
TABLE 3-2:
TABLE 3-3:
4004h
4004h
Note 1:
4064h
404Ch
4068h
405Ah
4059h
4058h
4054h
4058h
Note 1:
NVMCON
NVMCON
Value
Value
(1)
(1)
(1)
(1)
(1)
(1)
The destination address decides the
region (code memory or Configuration
register) of the erased rows/words.
The destination address decides the
region (code memory or Configuration
register) of the erased rows/words.
Write one Configuration register.
Program one row (32 instruction words)
of code memory or executive memory.
Erase the code memory and
Configuration registers (does not erase
programming executive code and
Device ID registers).
Erase the general segment and
Configuration bits associated with it.
Erase the boot segment and
Configuration bits associated with it.
Erase four rows of code memory.
Erase two rows of code memory.
Erase a row of code memory.
Erase all the Configuration registers
(except the code-protect fuses).
Erase Configuration registers except
FBS and FGS.
NVMCON VALUES FOR
ERASE OPERATIONS
NVMCON VALUES FOR
WRITE OPERATIONS
 2010 Microchip Technology Inc.
Write Operation
Erase Operation