PIC24F04KA200T-I/ST Microchip Technology, PIC24F04KA200T-I/ST Datasheet - Page 22

• Manufacturer Part Number: PIC24F04KA200T-I/ST
• Description: PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F04KA200T-I/ST

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (1.375K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC24FXXKA2XX
5.0
TABLE 5-1:
DS39991A-page 22
Standard Operating Conditions
Operating Temperature: 0C to +70C and programming: +25C is recommended.
D111
D112
D113
D031
D041
D042
D080
D090
D012
P1
P1A
P1B
P2
P3
P4
P4A
P5
P6
P7
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
Param
No.
V
I
I
V
V
V
V
V
C
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS
Symbol
PP
DDP
DLY
DD
IL
IH
IHH
OL
OH
PGC
PGCL
PGCH
SET
HLD
DLY
DLY
SET
HLD
DLY
DLY
DLY
DLY
R
VALID
DLY
HLD
KEY
KEY
IO
1
1
1
2
2
6
7
10
9
10
1
2
3
1
2
A
STANDARD OPERATING CONDITIONS
Supply Voltage During Programming
Programming Current on MCLR
Supply Current During Programming
Input Low Voltage
Input High Voltage
Programing Voltage on V
Output Low Voltage
Output High Voltage
Capacitive Loading on I/O Pin (PGDx)
Serial Clock (PGCx) Period
Serial Clock (PGCx) Low Time
Serial Clock (PGCx) High Time
Input Data Setup Time to Serial Clock 
Input Data Hold Time from PGCx
Delay Between 4-Bit Command and
Command Operand
Delay Between 4-Bit Command Operand
and the Next 4-Bit Command
Delay Between Last PGCx  of Command
Byte and First PGCx  of Read of Data
Word
V
Input Data Hold Time from MCLR  V
(from V
PGCx Low Time After Programming
Chip Erase Time
Page (4 rows) Erase Time
Row Programming Time
MCLR Rise Time to Enter ICSP™ mode
Data Out Valid from PGCx 
Delay Between Last PGCx  and MCLR 
MCLR to V
Delay Between First MCLR and First
PGCx for Key Sequence on PGDx
Delay Between Last PGCx for Key
Sequence on PGDx and Second MCLR 
DD
Setup Time to MCLR 
IHH
to V
DD
Characteristic
IH

)
PP
PP

V
V
0.8 V
DDCORE
DD
Min
V
125
100
400
1.4
—
—
—
—
50
50
15
15
40
40
20
25
—
10
—
2
5
5
0
1
1
SS
+1.5
DD
0.2 V
Max
3.60
V
100
0.4
1.0
50
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
9
DD
DD
Units
mA
A
ms
ms
ms
ms
ms
ms
pF
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
V
V
V
V
V
V
s
 2010 Microchip Technology Inc.
Normal programming
I
I
To meet AC specifications
OL
OH
= 8.5 mA @ 3.6V
= -3.0 mA @ 3.6V
Conditions
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