PIC24F04KA200T-I/ST Microchip Technology, PIC24F04KA200T-I/ST Datasheet - Page 3

• Manufacturer Part Number: PIC24F04KA200T-I/ST
• Description: PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F04KA200T-I/ST

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (1.375K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.2
The program memory map extends from 000000h to
FFFFFEh. Code storage is located at the base of the
memory map, and supports up to about 1.38 K words
of instructions (about 4 Kbytes).
memory map.
Table 2-2
number of program memory rows present in each
device variant.
The erase operation can be done on one word, half of
a row or one row at a time. The program operation can
be done only one word at a time.
The device Configuration registers are implemented
from location, F80000h to F80010h, and can be erased
or programmed one register at a time.
vides the implemented Configuration registers and
their locations.
Locations, FF0000h and FF0002h, are reserved for the
Device ID registers. These bits can be used by the
programmer to identify the device type that is being
programmed. See
information. The Device ID registers read out normally
even after code protection is applied.
TABLE 2-2:
TABLE 2-3:
 2010 Microchip Technology Inc.
PIC24F04KA200
PIC24F04KA201
FGS
FOSCSEL
FOSC
FWDT
FPOR
FICD
FDS
Configuration Register
Device
Memory Map
provides the program memory size and
PROGRAM MEMORY SIZES
CONFIGURATION REGISTER
LOCATIONS
Section 4.0 “Device ID”
(Instruction Words)
Program Memory
Upper Address
AFEh (1.375K)
Figure 2-2
Address
F8000A
F8000C
F8000E
F80004
F80006
F80008
F80010
Table 2-3
depicts the
for more
Rows
44
pro-
FIGURE 2-2:
PIC24FXXKA2XX
Configuration Registers
Diagnostic Words
(2816 x 24-bit)
Code Memory
User Flash
(2 x 16-bit)
Device ID
Reserved
Reserved
Reserved
Reserved
PROGRAM MEMORY MAP
DS39991A-page 3
000AFEh
000000h
800000h
8007EEh
8007F0h
8007FEh
800800h
FEFFFEh
FF0000h
FF0002h
FF0004h
FFFFFEh
F80000h
F80010h