PIC24F04KA200T-I/ST Microchip Technology, PIC24F04KA200T-I/ST Datasheet - Page 21

• Manufacturer Part Number: PIC24F04KA200T-I/ST
• Description: PIC24F Core, 4KB Flash, 512B RAM, 3V, Deep Sleep, 10-bit 500ksps ADC, CTMU, UART
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F04KA200T-I/ST

• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 12
• Program Memory Size: 4KB (1.375K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.0
The Device ID region of memory can be used to
determine the mask, variant and manufacturing
information about the device. The Device ID region is
2 x 16 bits and it can be read using the READC
command. This region of memory is read-only and can
also be read when code protection is enabled.
Table 4-1
Table 4-2
describes the bit field of each register.
TABLE 4-1:
TABLE 4-2:
TABLE 4-3:
TABLE 4-4:
 2010 Microchip Technology Inc.
PIC24F04KA200
PIC24F04KA201
FF0000h
FF0002h
FAMID<7:0>
DEV<7:0>
REV<3:0>
PIC24F04KAXXX
Legend: Item
Address
Device ID
Device
Bit Field
DEVICE ID
provides the Device ID registers;
provides the Device ID for each device;
SUM[a:b] =
CFGB
Byte sum of (FGS & 0x0003 + FOSCSEL & 0x0087 + FOSC & 0x00DF + FWDT & 0x00DF +
FPOR & 0x00FB + FICD & 0x00C3 + FDS & 0x00FF)
DEVREV
DEVID
Name
DEVICE IDs
PIC24FXXKA2XX DEVICE ID REGISTERS
DEVICE ID BITS DESCRIPTION
CHECKSUM COMPUTATION
=
Read Code Protection
Description
Byte sum of locations, a to b inclusive (all 3 bytes of code memory)
Configuration Block (masked),
Register
DEVREV
Disabled
15
Enabled
DEVID
DEVID
DEVID
0D02h
0D00h
14
13
FAMID<7:0>
Table 4-3
Encodes the revision number of the device.
Encodes the family ID of the device.
Encodes the individual ID of the device.
12
CFGB + SUM (0:000AFE)
Checksum Computation
11
10
—
0
4.1
4.1.1
Checksums for the PIC24FXXKA2XX family are
16 bits. The checksum is calculated by summing the
following:
• Contents of the code memory locations
• Contents of the Configuration registers
Table 4-4
each device.
All memory locations are summed, one byte at a time,
using only their native data size. More specifically,
Configuration registers are summed by adding the
lower two bytes of these locations (the upper byte is
ignored) while the code memory is summed by adding
all three bytes of the code memory.
9
Bit
8
Checksums
PIC24FXXKA2XX
describes how to calculate the checksum for
CHECKSUM COMPUTATION
Description
7
Checksum
Erased
0x74B4
0x0000
Value
6
5
DEV<7:0>
4
Chip Checksum with
0xAAAAAA at 0x00
at Last Location
Location and
3
DS39991A-page 21
0x72B6
0x0000
REV<3:0>
2
1
0