PIC18F87K90T-I/PT Microchip Technology, PIC18F87K90T-I/PT Datasheet - Page 298

• Manufacturer Part Number: PIC18F87K90T-I/PT
• Description: 128kB Flash, 4kB RAM, 1kB EE, 16MIPS, NanoWatt XLP, LCD, 5V 80 TQFP 12x12x1mm T/
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F87K90T-I/PT

• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 128 KB
• Data Ram Size: 4 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 64 MHz
• Number Of Timers: 11
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 64MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 69
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Details

PIC18F87K90 FAMILY
20.9
The LCD timing generation provides an interrupt that
defines the LCD frame timing. This interrupt can be
used to coordinate the writing of the pixel data with the
start of a new frame, which produces a visually crisp
transition of the image.
This interrupt can also be used to synchronize external
events to the LCD. For example, the interface to an
external segment driver can be synchronized for
segment data updates to the LCD frame.
A new frame is defined as beginning at the leading
edge of the COM0 common signal. The interrupt will be
set immediately after the LCD controller completes
accessing all pixel data required for a frame. This will
occur at a fixed interval before the frame boundary
(T
The LCD controller will begin to access data for the
next frame within the interval from the interrupt to when
the controller begins accessing data after the interrupt
(T
is when the LCD controller will begin to access the data
for the next frame.
FIGURE 20-18:
DS39957D-page 298
FINT
FWR
), as shown in
). New data must be written within T
COM0
COM1
COM2
COM3
T
T
FWR
FINT
LCD Interrupts
= T
= (T
(T
FRAME
FWR
FWR
/2 – (2 T
/2 – (1 T
Figure
Boundary
/2*(LMUX<1:0> + 1) + T
Frame
EXAMPLE WAVEFORMS AND INTERRUPT TIMING IN QUARTER DUTY
CYCLE DRIVE
CY
CY
20-18.
+ 40 ns)) minimum = 1.5(T
+ 40 ns)) maximum = 1.5(T
FWR
CY
/2
, as this
2 Frames
FRAME
FRAME
Boundary
Frame
/4) – (2 T
/4) – (1 T
When the LCD driver is running with Type-B waveforms
and the LMUX<1:0> bits are not equal to ‘00’, there are
some additional issues.
Since the DC voltage on the pixel takes two frames to
maintain 0V, the pixel data must not change between
subsequent frames. If the pixel data were allowed to
change, the waveform for the odd frames would not
necessarily be the complement of the waveform gener-
ated in the even frames and a DC component would be
introduced into the panel.
Because of this, using Type-B waveforms requires
synchronizing the LCD pixel updates to occur within a
subframe after the frame interrupt.
To correctly sequence writing in Type-B, the interrupt
only occurs on complete phase intervals. If the user
attempts to write when the write is disabled, the WERR
bit (LCDCON<5>) is set.
Note:
CY
CY
LCD
Interrupt
Occurs
+ 40 ns)
+ 40 ns)
The interrupt is not generated when the
Type-A waveform is selected and when
the Type-B with no multiplex (static) is
selected.
T
FWR
T
 2009-2011 Microchip Technology Inc.
FINT
Controller Accesses
Next Frame Data
Boundary
Frame
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
3
2
1
0
3
2
1
0
3
2
1
0
3
2
1
0