PIC18F23K20-E/SP Microchip Technology, PIC18F23K20-E/SP Datasheet - Page 223

• Manufacturer Part Number: PIC18F23K20-E/SP
• Description: 8 KB Enh Flash, 768 RAM, 25 I/O Pb Free, Nanowatt XLP 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F23K20-E/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.4.8
To initiate a Start condition, the user sets the Start
Enable bit, SEN bit of the SSPCON2 register. If the
SDA and SCL pins are sampled high, the Baud Rate
Generator
SSPADD<6:0> and starts its count. If SCL and SDA are
both sampled high when the Baud Rate Generator
times out (T
of the SDA being driven low while SCL is high is the
Start condition and causes the S bit of the SSPSTAT1
register to be set. Following this, the Baud Rate Gener-
ator is reloaded with the contents of SSPADD<7:0>
and resumes its count. When the Baud Rate Generator
times out (T
will be automatically cleared by hardware; the Baud
Rate Generator is suspended, leaving the SDA line
held low and the Start condition is complete.
FIGURE 17-19:
 2010 Microchip Technology Inc.
BRG
I
CONDITION TIMING
BRG
2
is
C MASTER MODE START
), the SEN bit of the SSPCON2 register
), the SDA pin is driven low. The action
reloaded
Write to SEN bit occurs here
FIRST START BIT TIMING
with
SDA
SCL
the
contents
SDA = 1,
SCL = 1
T
BRG
of
Set S bit (SSPSTAT<3>)
T
S
BRG
At completion of Start bit,
hardware clears SEN bit
17.4.8.1
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
PIC18F2XK20/4XK20
and sets SSPIF bit
Note:
Note:
T
Write to SSPBUF occurs here
BRG
1st bit
If at the beginning of the Start condition,
the SDA and SCL pins are already sam-
pled low, or if during the Start condition, the
SCL line is sampled low before the SDA
line is driven low, a bus collision occurs,
the Bus Collision Interrupt Flag, BCLIF, is
set, the Start condition is aborted and the
I
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
2
C module is reset into its Idle state.
WCOL Status Flag
T
BRG
2nd bit
DS41303G-page 223