PIC18F2221-E/SO Microchip Technology, PIC18F2221-E/SO Datasheet - Page 80

• Manufacturer Part Number: PIC18F2221-E/SO
• Description: 4KB, Flash, 512bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIC18F2221/2321/4221/4321 FAMILY
FIGURE 7-2:
7.2
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include the:
• EECON1 register
• EECON2 register
• TABLAT register
• TBLPTR registers
7.2.1
The EECON1 register (Register 7-1) is the control
register for memory accesses. The EECON2 register is
not a physical register; it is used exclusively in the
memory
EECON2 will read all ‘0’s.
The EEPGD control bit determines if the access will be
a program or data EEPROM memory access. When
clear, any subsequent operations will operate on the
data EEPROM memory. When set, any subsequent
operations will operate on the program memory.
The CFGS control bit determines if the access will be
to the Configuration/Calibration registers or to program
memory/data
subsequent operations will operate on Configuration
registers regardless of EEPGD (see Section 24.0
“Special Features of the CPU”). When clear, memory
selection access is determined by EEPGD.
DS39689F-page 80
Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by
Control Registers
write
TBLPTRU
EECON1 AND EECON2 REGISTERS
EEPROM
TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in
Section 7.5 “Writing to Flash Program Memory”.
and
Table Pointer
TABLE WRITE OPERATION
TBLPTRH
erase
memory.
sequences.
(1)
TBLPTRL
Program Memory
(TBLPTR)
When
Reading
set,
Instruction: TBLWT*
Holding Registers
Program Memory
The FREE bit, when set, will allow a program memory
erase operation. When FREE is set, the erase
operation is initiated on the next WR command. When
FREE is clear, only writes are enabled.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set in hardware when the WR bit is set and cleared
when the internal programming timer expires and the
write operation is complete.
The WR control bit initiates write operations. The bit
cannot be cleared, only set, in software; it is cleared in
hardware at the completion of the write operation.
Note:
Note:
During normal operation, the WRERR bit
may read as ‘1’. This can indicate that a
write operation was prematurely termi-
nated by a Reset, or a write operation was
attempted improperly.
The EEIF interrupt flag bit (PIR2<4>) is set
when the write is complete. It must be
cleared in software.
© 2009 Microchip Technology Inc.
Table Latch (8-bit)
TABLAT