PIC18F2221-E/SO Microchip Technology, PIC18F2221-E/SO Datasheet - Page 173

• Manufacturer Part Number: PIC18F2221-E/SO
• Description: 4KB, Flash, 512bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

18.3.6
In Slave mode, the data is transmitted and received as
the external clock pulses appear on SCK. When the
last bit is latched, the SSPIF interrupt flag bit is set.
Before enabling the module in SPI Slave mode, the
clock line must match the proper Idle state. The clock
line can be observed by reading the SCK pin. The Idle
state is determined by the CKP bit (SSPCON1<4>).
While in Slave mode, the external clock is supplied by
the external clock source on the SCK pin. This external
clock must meet the minimum high and low times as
specified in the electrical specifications.
While in Sleep mode, the slave can transmit/receive
data. When a byte is received, the device will wake-up
from Sleep.
18.3.7
The SS pin allows a Synchronous Slave mode. The SPI
operation must be in Slave mode with the SS pin control
enabled (SSPCON1<3:0> = 04h). When the SS pin is
low, transmission and reception are enabled and the
FIGURE 18-4:
© 2009 Microchip Technology Inc.
SS
SCK
(CKP = 0
CKE = 0)
SCK
(CKP = 1
CKE = 0)
Write to
SSPBUF
SDO
SDI
(SMP = 0)
Input
Sample
(SMP = 0)
SSPIF
Interrupt
Flag
SSPSR to
SSPBUF
SLAVE MODE
SLAVE SELECT
SYNCHRONIZATION
SLAVE SYNCHRONIZATION WAVEFORM
PIC18F2221/2321/4221/4321 FAMILY
bit 7
bit 7
bit 6
SDO pin is driven. When the SS pin goes high, the SDO
pin is no longer driven, even if in the middle of a
transmitted byte and becomes a floating output. External
pull-up/pull-down resistors may be desirable depending
on the application.
When the SPI module resets, the bit counter is forced
to ‘0’. This can be done by either forcing the SS pin to
a high level or clearing the SSPEN bit.
To emulate two-wire communication, the SDO pin can
be connected to the SDI pin. When the SPI needs to
operate as a receiver, the SDO pin can be configured
as an input. This disables transmissions from the SDO.
The SDI can always be left as an input (SDI function)
since it cannot create a bus conflict.
Note 1: When the SPI interface is in Slave mode
2: If the SPI interface is used in Slave mode
with
(SSPCON1<3:0> = 0100), the SPI module
will reset if the SS pin is set to V
with CKE set, then the SS pin control
must be enabled.
bit 7
bit 7
SS
pin
Next Q4 Cycle
after Q2↓
control
DS39689F-page 173
bit 0
bit 0
DD
enabled
.