PIC18F2221-E/SO Microchip Technology, PIC18F2221-E/SO Datasheet - Page 43

• Manufacturer Part Number: PIC18F2221-E/SO
• Description: 4KB, Flash, 512bytes-RAM, 25I/O, 8-bit Family,nanoWatt 28 SOIC .300in TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F2221-E/SO

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC (7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3
The power-managed Sleep mode in the PIC18F2221/
2321/4221/4321 family devices is identical to the leg-
acy Sleep mode offered in all other PIC devices. It is
entered by clearing the IDLEN bit (the default state on
device Reset) and executing the SLEEP instruction.
This shuts down the selected oscillator (Figure 4-5). All
clock source status bits are cleared.
Entering the Sleep mode from any other mode does not
require a clock switch. This is because no clocks are
needed once the controller has entered Sleep. If the
WDT is selected, the INTRC source will continue to
operate. If the Timer1 oscillator is enabled, it will also
continue to run.
When a wake event occurs in Sleep mode (by interrupt,
Reset or WDT time-out), the device will not be clocked
until the clock source selected by the SCS<1:0> bits
becomes ready (see Figure 4-6), or it will be clocked
from the internal oscillator block if either the Two-Speed
Start-up or the Fail-Safe Clock Monitor are enabled
(see Section 24.0 “Special Features of the CPU”). In
either case, the OSTS bit is set when the primary clock
is providing the device clocks. The IDLEN and SCS bits
are not affected by the wake-up.
FIGURE 4-5:
FIGURE 4-6:
© 2009 Microchip Technology Inc.
Peripheral
Program
Counter
OSC1
Clock
Clock
Sleep
CPU
Note1: T
CPU Clock
Peripheral
PLL Clock
Program
Sleep Mode
Counter
Output
OSC1
Clock
Q1
OST
Q2
PC
= 1024 T
Q3
Wake Event
Q4
TRANSITION TIMING FOR ENTRY TO SLEEP MODE
TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL)
PIC18F2221/2321/4221/4321 FAMILY
OSC
Q1
; T
Q1
PLL
T
OST
= 2 ms (approx). These intervals are not shown to scale.
(1)
PC
T
PLL
OSTS bit Set
(1)
Q2 Q3 Q4 Q1 Q2
4.4
The Idle modes allow the controller’s CPU to be
selectively shut down while the peripherals continue to
operate. Selecting a particular Idle mode allows users
to further manage power consumption.
If the IDLEN bit is set to a ‘1’ when a SLEEP instruction is
executed, the peripherals will be clocked from the clock
source selected using the SCS<1:0> bits; however, the
CPU will not be clocked. The clock source status bits are
not affected. Setting IDLEN and executing a SLEEP
instruction provides a quick method of switching from a
given Run mode to its corresponding Idle mode.
If the WDT is selected, the INTRC source will continue
to operate. If the Timer1 oscillator is enabled, it will also
continue to run.
Since the CPU is not executing instructions, the only
exits from any of the Idle modes are by interrupt, WDT
time-out or a Reset. When a wake event occurs, CPU
execution is delayed by an interval of T
(parameter 38, Table 27-10) while it becomes ready to
execute code. When the CPU begins executing code,
it resumes with the same clock source for the current
Idle mode. For example, when waking from RC_IDLE
mode, the internal oscillator block will clock the CPU
and peripherals (in other words, RC_RUN mode). The
IDLEN and SCS bits are not affected by the wake-up.
While in any Idle mode or the Sleep mode, a WDT
time-out will result in a WDT wake-up to the Run mode
currently specified by the SCS<1:0> bits.
PC + 2
PC + 2
Q3 Q4 Q1 Q2
Idle Modes
PC + 4
Q3 Q4
Q1 Q2 Q3 Q4
PC + 6
DS39689F-page 43
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