PIC16F1518-E/SP Microchip Technology, PIC16F1518-E/SP Datasheet - Page 233

• Manufacturer Part Number: PIC16F1518-E/SP
• Description: 28-pin, 28KB Flash, 1024B RAM, 10-bit ADC, 2xCCP, SPI, MI2C, EUSART, 2.3V-5.5V 2
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1518-E/SP

• Processor Series: PIC16F151x
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Package / Case: PDIP-28
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

REGISTER 21-2:
 2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3-0
Note
R/C/HS-0/0
WCOL
1:
2:
3:
4:
5:
In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register.
When enabled, these pins must be properly configured as input or output.
When enabled, the SDA and SCL pins must be configured as inputs.
SSPADD values of 0, 1 or 2 are not supported for I
SSPADD value of ‘0’ is not supported. Use SSPM = 0000 instead.
WCOL: Write Collision Detect bit
Master mode:
1 =
0 =
Slave mode:
1 =
0 =
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 =
0 =
In I
1 =
0 =
SSPEN: Synchronous Serial Port Enable bit
In both modes, when enabled, these pins must be properly configured as input or output
In SPI mode:
1 =
0 =
In I
1 =
0 =
CKP: Clock Polarity Select bit
In SPI mode:
1 = Idle state for clock is a high level
0 = Idle state for clock is a low level
In I
SCL release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
In I
Unused in this mode
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = F
0001 = SPI Master mode, clock = F
0010 = SPI Master mode, clock = F
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin, SS pin control enabled
0101 = SPI Slave mode, clock = SCK pin, SS pin control disabled, SS can be used as I/O pin
0110 = I
0111 = I
1000 = I
1001 = Reserved
1010 = SPI Master mode, clock = F
1011 = I
1100 = Reserved
1101 = Reserved
1110 = I
1111 = I
R/C/HS-0/0
2
2
2
2
C mode:
C mode:
C Slave mode:
C Master mode:
SSPOV
A write to the SSPBUF register was attempted while the I
No collision
The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software)
No collision
A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost.
Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid
setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the
SSPBUF register (must be cleared in software).
No overflow
A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a “don’t care” in Transmit mode
(must be cleared in software).
No overflow
Enables serial port and configures SCK, SDO, SDI and SS as the source of the serial port pins
Disables serial port and configures these pins as I/O port pins
Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins
Disables serial port and configures these pins as I/O port pins
SSPCON1: SSP CONTROL REGISTER 1
2
2
2
2
2
2
C Slave mode, 7-bit address
C Slave mode, 10-bit address
C Master mode, clock = F
C firmware controlled Master mode (Slave idle)
C Slave mode, 7-bit address with Start and Stop bit interrupts enabled
C Slave mode, 10-bit address with Start and Stop bit interrupts enabled
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
SSPEN
OSC
OSC
OSC
OSC
OSC
(1)
/4
/16
/64
/(4 * (SSPADD+1))
/ (4 * (SSPADD+1))
R/W-0/0
CKP
Preliminary
2
C Mode.
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HS = Bit is set by hardware
(5)
R/W-0/0
(4)
2
PIC16(L)F1516/7/8/9
C conditions were not valid for a transmission to be started
R/W-0/0
SSPM<3:0>
C = User cleared
(2)
(3)
R/W-0/0
DS41452B-page 233
R/W-0/0
bit 0