PIC16F1518-E/SP Microchip Technology, PIC16F1518-E/SP Datasheet - Page 106
![28-pin, 28KB Flash, 1024B RAM, 10-bit ADC, 2xCCP, SPI, MI2C, EUSART, 2.3V-5.5V 2](/photos/16/11/161110/pdip28_sml.jpg)
PIC16F1518-E/SP
Manufacturer Part Number
PIC16F1518-E/SP
Description
28-pin, 28KB Flash, 1024B RAM, 10-bit ADC, 2xCCP, SPI, MI2C, EUSART, 2.3V-5.5V 2
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F1516-EMV.pdf
(344 pages)
Specifications of PIC16F1518-E/SP
Processor Series
PIC16F151x
Core
PIC
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
16 KB
Data Ram Size
1 KB
Interface Type
I2C, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
25
Number Of Timers
3
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
Through Hole
Package / Case
PDIP-28
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Eeprom Size
-
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 5.5 V
Data Converters
A/D 17x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Lead Free Status / Rohs Status
Details
- Current page: 106 of 344
- Download datasheet (3Mb)
PIC16(L)F1516/7/8/9
EXAMPLE 11-3:
DS41452B-page 106
; This write routine assumes the following:
; 1. 64 bytes of data are loaded, starting at the address in DATA_ADDR
; 2. Each word of data to be written is made up of two adjacent bytes in DATA_ADDR,
; stored in little endian format
; 3. A valid starting address (the least significant bits = 00000) is loaded in ADDRH:ADDRL
; 4. ADDRH and ADDRL are located in shared data memory 0x70 - 0x7F (common RAM)
;
LOOP
START_WRITE
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
MOVLW
MOVWF
MOVLW
MOVWF
BCF
BSF
BSF
MOVIW
MOVWF
MOVIW
MOVWF
MOVF
XORLW
ANDLW
BTFSC
GOTO
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
INCF
GOTO
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BCF
BSF
WRITING TO FLASH PROGRAM MEMORY
INTCON,GIE
PMADRH
ADDRH,W
PMADRH
ADDRL,W
PMADRL
LOW DATA_ADDR
FSR0L
HIGH DATA_ADDR ; Load initial data address
FSR0H
PMCON1,CFGS
PMCON1,WREN
PMCON1,LWLO
FSR0++
PMDATL
FSR0++
PMDATH
PMADRL,W
0x1F
0x1F
STATUS,Z
START_WRITE
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
PMADRL,F
LOOP
PMCON1,LWLO
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
PMCON1,WREN
INTCON,GIE
; Disable ints so required sequences will execute properly
; Bank 3
; Load initial address
;
;
;
; Load initial data address
;
;
; Not configuration space
; Enable writes
; Only Load Write Latches
; Load first data byte into lower
;
; Load second data byte into upper
;
; Check if lower bits of address are '00000'
; Check if we're on the last of 32 addresses
;
; Exit if last of 32 words,
;
; Start of required write sequence:
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; NOP instructions are forced as processor
; loads program memory write latches
;
; Still loading latches Increment address
; Write next latches
; No more loading latches - Actually start Flash program
; memory write
; Start of required write sequence:
; Write 55h
;
; Write AAh
; Set WR bit to begin write
; NOP instructions are forced as processor writes
; all the program memory write latches simultaneously
; to program memory.
; After NOPs, the processor
; stalls until the self-write process in complete
; after write processor continues with 3rd instruction
; Disable writes
; Enable interrupts
Preliminary
2011 Microchip Technology Inc.
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