PIC12LF1840-I/MF Microchip Technology, PIC12LF1840-I/MF Datasheet - Page 42
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano](/photos/16/0/160077/dfn8_sml.jpg)
PIC12LF1840-I/MF
Manufacturer Part Number
PIC12LF1840-I/MF
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano
Manufacturer
Microchip Technology
Datasheet
1.PIC12F1840-IP.pdf
(382 pages)
Specifications of PIC12LF1840-I/MF
Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
DFN-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1840-I/MF
Manufacturer:
MICROCHIP
Quantity:
887
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- Download datasheet (4Mb)
PIC12(L)F1840
REGISTER 4-1:
DS41441B-page 42
bit 13
bit 6
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 13
bit 12
bit 11
bit 10-9
bit 8
bit 7
bit 6
bit 5
bit 4-3
Note 1:
FCMEN
R/P-1/1
R/P-1/1
MCLRE
2:
3:
Enabling Brown-out Reset does not automatically enable Power-up Timer.
The entire data EEPROM will be erased when the code protection is turned off during an erase.
The entire program memory will be erased when the code protection is turned off.
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor is enabled
0 = Fail-Safe Clock Monitor is disabled
IESO: Internal External Switchover bit
1 = Internal/External Switchover mode is enabled
0 = Internal/External Switchover mode is disabled
CLKOUTEN: Clock Out Enable bit
If FOSC Configuration bits are set to LP, XT, HS modes:
All other FOSC modes:
BOREN<1:0>: Brown-out Reset Enable bits
11 = BOR enabled
10 = BOR enabled during operation and disabled in Sleep
01 = BOR controlled by SBOREN bit of the BORCON register
00 = BOR disabled
CPD: Data Code Protection bit
1 = Data memory code protection is disabled
0 = Data memory code protection is enabled
CP: Code Protection bit
1 = Program memory code protection is disabled
0 = Program memory code protection is enabled
MCLRE: RA3/MCLR/V
If LVP bit = 1:
If LVP bit = 0:
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE<1:0>: Watchdog Timer Enable bit
11 = WDT enabled
10 = WDT enabled while running and disabled in Sleep
01 = WDT controlled by the SWDTEN bit in the WDTCON register
00 = WDT disabled
This bit is ignored.
1 = MCLR/V
0 = MCLR/V
This bit is ignored, CLKOUT function is disabled. Oscillator function on the CLKOUT pin.
PWRTE
R/P-1/1
R/P-1/1
1 = CLKOUT function is disabled. I/O function on the CLKOUT pin.
0 = CLKOUT function is enabled on the CLKOUT pin
CONFIGURATION WORD 1
IESO
WPUA register.
PP
PP
W = Writable bit
‘0’ = Bit is cleared
x = Bit is unknown
pin function is MCLR; Weak pull-up enabled.
pin function is digital input; MCLR internally disabled; Weak pull-up under control of
CLKOUTEN
PP
R/P-1/1
R/P-1/1
WDTE1
(3)
Pin Function Select bit
(2)
(1)
Preliminary
BOREN1
WDTE0
R/P-1/1
R/P-1/1
(1)
U = Unimplemented bit, read as ‘1’
-n/n = Value at POR and BOR/Value at all other Resets
P = Programmable bit
BOREN0
R/P-1/1
R/P-1/1
FOSC2
2011 Microchip Technology Inc.
R/P-1/1
R/P-1/1
FOSC1
CPD
R/P-1/1
R/P-1/1
FOSC0
CP
bit 7
bit 0
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