PIC12LF1840-I/MF Microchip Technology, PIC12LF1840-I/MF Datasheet - Page 200
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano](/photos/16/0/160077/dfn8_sml.jpg)
PIC12LF1840-I/MF
Manufacturer Part Number
PIC12LF1840-I/MF
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano
Manufacturer
Microchip Technology
Datasheet
1.PIC12F1840-IP.pdf
(382 pages)
Specifications of PIC12LF1840-I/MF
Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
DFN-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1840-I/MF
Manufacturer:
MICROCHIP
Quantity:
887
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PIC12(L)F1840
24.4.1
In Half-Bridge mode, two pins are used as outputs to
drive push-pull loads. The PWM output signal is output
on the CCP1/P1A pin, while the complementary PWM
output signal is output on the P1B pin (see
This mode can be used for Half-Bridge applications, as
shown in
where four power switches are being modulated with
two PWM signals.
In Half-Bridge mode, the programmable dead-band delay
can be used to prevent shoot-through current in Half-
Bridge power devices. The value of the P1DC<6:0> bits
of the PWM1CON register sets the number of instruction
cycles before the output is driven active. If the value is
greater than the duty cycle, the corresponding output
remains
Section 24.4.4 “Programmable Dead-Band Delay
Mode”
operations.
FIGURE 24-9:
DS41441B-page 200
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
for more details of the dead-band delay
Figure
inactive
HALF-BRIDGE MODE
24-9, or for Full-Bridge applications,
during
EXAMPLE OF HALF-BRIDGE APPLICATIONS
the
P1A
P1B
entire
Figure
cycle.
P1A
P1B
FET
Driver
FET
Driver
24-9).
See
Preliminary
FET
Driver
FET
Driver
Since the P1A and P1B outputs are multiplexed with
the PORT data latches, the associated TRIS bits must
be cleared to configure P1A and P1B as outputs.
FIGURE 24-8:
P1A
P1B
td = Dead-Band Delay
Note 1: At this time, the TMR2 register is equal to the
Load
V+
(2)
(2)
2: Output signals are shown as active-high.
(1)
PR2 register.
td
Pulse Width
Load
Period
td
FET
Driver
FET
Driver
EXAMPLE OF HALF-
BRIDGE PWM OUTPUT
2011 Microchip Technology Inc.
+
-
+
-
(1)
Period
(1)
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