PIC12LF1840-I/MF Microchip Technology, PIC12LF1840-I/MF Datasheet - Page 255
![7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano](/photos/16/0/160077/dfn8_sml.jpg)
PIC12LF1840-I/MF
Manufacturer Part Number
PIC12LF1840-I/MF
Description
7 KB Flash, 256 Bytes RAM, 32 MHz Int. Osc, 6 I/0, Enhanced Mid Range Core, Nano
Manufacturer
Microchip Technology
Datasheet
1.PIC12F1840-IP.pdf
(382 pages)
Specifications of PIC12LF1840-I/MF
Processor Series
PIC12F
Core
PIC
Program Memory Type
Flash
Program Memory Size
7 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
3
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
DFN-8
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12LF1840-I/MF
Manufacturer:
MICROCHIP
Quantity:
887
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FIGURE 25-34:
FIGURE 25-35:
2011 Microchip Technology Inc.
SDA
SCL
SEN
S
BCL1IF
SSP1IF
S
BCL1IF
SSP1IF
SDA
SCL
SEN
BUS COLLISION DURING START CONDITION (SCL = 0)
BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION
SDA pulled low by other master.
Reset BRG and assert SDA.
’0’
’0’
SCL = 0 before BRG time-out,
bus collision occurs. Set BCL1IF.
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
Less than T
BRG
SDA = 0, SCL = 1
SDA = 0, SCL = 1
Preliminary
SDA = 0, SCL = 1,
set SSP1IF
T
Set SEN, enable Start
sequence if SDA = 1, SCL = 1
BRG
S
Set S
T
BRG
T
BRG
Set SSP1IF
SCL = 0 before SDA = 0,
bus collision occurs. Set BCL1IF.
SCL pulled low after BRG
time-out
PIC12(L)F1840
Interrupt cleared
by software
Interrupts cleared
by software
’0’
’0’
’0’
DS41441B-page 255
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