XC5VLX50-1FFG324C Xilinx Inc, XC5VLX50-1FFG324C Datasheet - Page 297
![FPGA, VIRTEX-5 LX, 50K, 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-1FFG324C
Manufacturer Part Number
XC5VLX50-1FFG324C
Description
FPGA, VIRTEX-5 LX, 50K, 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FFG324C
No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
1769472
No. Of I/o's
220
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1562
Available stocks
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- XC5VLX30-1FFG324C PDF datasheet
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Differential LVPECL (Low-Voltage Positive Emitter-Coupled Logic)
LVPECL Transceiver Termination
LVPECL is a very popular and powerful high-speed interface in many system applications.
Virtex-5 FPGA I/Os are designed to comply with the EIA/TIA electrical specifications for
2.5V LVPECL to make system and board design easier.
The Virtex-5 FPGA LVPECL transmitter and receiver requires the termination shown in
Figure
50 Ω transmission lines. The LVPECL driver is composed of two LVCMOS drivers that
form a compliant LVPECL output when combined with the three resistor output
termination circuit.
X-Ref Target - Figure 6-90
LVPECL_25
LVPECL_25
6-90, illustrating a Virtex-5 FPGA LVPECL transmitter and receiver on a board with
IOB
Figure 6-90: LVPECL Transmitter Termination
www.xilinx.com
70Ω
70Ω
R
R
S
S
R DIV
187Ω
Specific Guidelines for I/O Supported Standards
Z 0 = 50Ω
Z 0 = 50Ω
R DIFF = 100Ω
INX
IN
IOB
LVPECL_25
+
-
ug190_6_84_030506
Data in
297
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