XC5VLX50-1FFG324C Xilinx Inc, XC5VLX50-1FFG324C Datasheet - Page 250
![FPGA, VIRTEX-5 LX, 50K, 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-1FFG324C
Manufacturer Part Number
XC5VLX50-1FFG324C
Description
FPGA, VIRTEX-5 LX, 50K, 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FFG324C
No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
1769472
No. Of I/o's
220
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1562
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Chapter 6: SelectIO Resources
250
HSTL (High-Speed Transceiver Logic)
HSTL_ I, HSTL_ III, HSTL_ I_18, HSTL_ III_18, HSTL_I_12
HSTL_ I_DCI, HSTL_ III_DCI, HSTL_ I_DCI_18, HSTL_ III_DCI_18
HSTL_ II, HSTL_ IV, HSTL_ II_18, HSTL_ IV_18
Table 6-14
Table 6-14: GTLP DC Voltage Specifications
The High-Speed Transceiver Logic (HSTL) standard is a general-purpose high-speed bus
standard sponsored by IBM (EIA/JESD8-6). The 1.5V and 1.8V have four variations or
classes. To support clocking high-speed memory interfaces, a differential version of this
standard was added. Virtex-5 FPGA I/O supports all four classes for 1.5V and 1.8V and the
differential versions of classes I and II. These differential versions of the standard require a
differential amplifier input buffer and a push-pull output buffer.
HSTL_I uses V
parallel termination voltage (V
unidirectional links.
HSTL_I_DCI provides on-chip split thevenin termination powered from V
equivalent parallel termination voltage (V
single termination powered from V
be used in unidirectional links.
HSTL_II uses V
parallel termination voltage (V
bidirectional links.
Notes:
1. N must be greater than or equal to 0.653 and less than or equal to 0.68.
V
V
V
V
V
V
V
I
I
I
OH
OL
OL
CCO
REF
TT
IH
IL
OH
OL
at V
at V
= V
= V
at V
= N × V
REF
REF
OL
OL
OH
lists the GTLP DC voltage specifications.
(mA) at 0.6V
(mA) at 0.3V
– 0.1
+ 0.1
(mA)
TT
CCO
CCO
(1)
/2 as a parallel termination voltage (V
/2 as a parallel termination voltage (V
www.xilinx.com
TT
TT
). HSTL_I and HSTL_III are intended to be used in
). HSTL_II and HSTL_IV are intended to be used in
CCO
. HSTL_I_DCI and HSTL_III_DCI are intended to
TT
) of V
Min
0.88
1.35
0.98
0.3
36
–
–
–
–
–
CCO
/2. HSTL_III_DCI provides on-chip
TT
TT
). HSTL_III uses V
). HSTL_IV uses V
Typ
0.45
1.0
1.5
1.1
0.9
–
–
–
–
–
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
CCO
Max
1.12
1.65
1.02
0.6
48
–
–
–
–
–
, creating an
CCO
CCO
as a
as a
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