XC5VLX50-1FFG324C Xilinx Inc, XC5VLX50-1FFG324C Datasheet - Page 142

• Manufacturer Part Number: XC5VLX50-1FFG324C
• Description: FPGA, VIRTEX-5 LX, 50K, 324FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX50-1FFG324C

• No. Of Logic Blocks: 7200
• Family Type: Virtex-5
• No. Of Speed Grades: 1
• Total Ram Bits: 1769472
• No. Of I/o's: 220
• Clock Management: DCM, PLL
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 550MHz
• Number Of Logic Elements/cells: 46080
• Number Of Labs/clbs: 3600
• Number Of I /o: 220
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 324-BBGA, FCBGA
• Core Supply Voltage Range: 1V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1562

Chapter 4: Block RAM
FIFO Architecture: a Top-Level View
FIFO Primitives
142
Figure 4-17
write pointer, and status flag logic are dedicated for FIFO use only.
X-Ref Target - Figure 4-17
Figure 4-18
X-Ref Target - Figure 4-18
WRCOUNT
DIN/DINP
WRCLK
WREN
shows a top-level view of the Virtex-5 FIFO architecture. The read pointer,
shows the FIFO36 primitive.
RST
Figure 4-17: Top-Level View of FIFO in Block RAM
Pointer
Write
www.xilinx.com
Figure 4-18: FIFO36 Primitive
DI[31:0]
DIP[3:0]
RDEN
RDCLK
WREN
WRCLK
RST
waddr
Status Flag
Block
Logic
FIFO36
RAM
WRCOUNT[12:0]
ALMOSTEMPTY
RDCOUNT[12:0]
ALMOSTFULL
DOP[3:0]
DO[31:0]
WRERR
RDERR
EMPTY
raddr
FULL
ug190_4_15_021107
Pointer
Read
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
RDCOUNT
DO/DOP
RDCLK
RDEN
ug190_4_27_061906