XC5VLX50-1FFG324C Xilinx Inc, XC5VLX50-1FFG324C Datasheet - Page 209
![FPGA, VIRTEX-5 LX, 50K, 324FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX50-1FFG324C
Manufacturer Part Number
XC5VLX50-1FFG324C
Description
FPGA, VIRTEX-5 LX, 50K, 324FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX50-1FFG324C
No. Of Logic Blocks
7200
Family Type
Virtex-5
No. Of Speed Grades
1
Total Ram Bits
1769472
No. Of I/o's
220
Clock Management
DCM, PLL
I/o Supply Voltage
3.3V
Operating Frequency Max
550MHz
Number Of Logic Elements/cells
46080
Number Of Labs/clbs
3600
Number Of I /o
220
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
324-BBGA, FCBGA
Core Supply Voltage Range
1V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML561-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML550-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-V5-ML521-UNI-G - EVALUATION PLATFORM VIRTEX-5HW-AFX-FF324-500-G - BOARD DEV VIRTEX 5 FF324HW-V5GBE-DK-UNI-G - KIT DEV V5 LXT GIGABIT ETHERNET122-1508 - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
122-1562
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX50-1FFG324C
Manufacturer:
XILINX
Quantity:
101
Company:
Part Number:
XC5VLX50-1FFG324C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC5VLX50-1FFG324C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Company:
Part Number:
XC5VLX50-1FFG324CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
- XC5VLX30-1FFG324C PDF datasheet
- XC5VLX30-1FFG324C PDF datasheet #2
- XC5VLX30-1FFG324C PDF datasheet #3
- Current page: 209 of 385
- Download datasheet (14Mb)
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Clock Event 1: Shift In
During a write (Shift In) operation, the single-bit content of the register at the address on
the A/B/C/D inputs is changed, as data is shifted through the SRL. The data written to
this register is reflected on the A/B/C/D outputs synchronously, if the address is
unchanged during the clock event. If the A/B/C/D inputs are changed during a clock
event, the value of the data at the addressable output (A/B/C/D outputs) is invalid.
•
•
Clock Event 2: Shift In
•
Clock Event 3: Shift In/Addressable (Asynchronous) READ
All Read operations are asynchronous to the CLK signal. If the address is changed
(between clock events), the contents of the register at that address are reflected at the
addressable output (A/B/C/D outputs) after a delay of length T
through a LUT).
•
•
Clock Event 32: MSB (Most Significant Bit) Changes
At time T
in this case) on the DMUX output of the slice via the MC31 output of LUT A (SRL). This is
also applicable to the AMUX, BMUX, CMUX, DMUX, and COUT outputs at time T
T
WOSCO
At time T
enabling the SRL for the Write operation that follows.
At time T
and is reflected on the A/B/C/D output after a delay of length T
1. Since the address 0 is specified at clock event 1, the data on the DI input is reflected
at A/B/C/D output, because it is written to register 0.
At time T
and is reflected on the A/B/C/D output after a delay of length T
2. Since the address 0 is still specified at clock event 2, the data on the DI input is
reflected at the D output, because it is written to register 0.
At time T
and is reflected on the A/B/C/D output T
The address is changed (from 0 to 2). The value stored in register 2 at this time is a 0
(in this example, this was the first data shifted in), and it is reflected on the A/B/C/D
output after a delay of length T
after clock event 1.
REG
WS
DS
DS
DS
after clock event 32, the first bit shifted into the SRL becomes valid (logical 0
before clock event 1 the data becomes valid (0) at the DI input of the SRL
before clock event 2, the data becomes valid (1) at the DI input of the SRL
before clock event 3, the data becomes valid (1) at the DI input of the SRL
before clock event 1, the write-enable signal (WE) becomes valid-High,
www.xilinx.com
ILO
.
REG
time after clock event 3.
CLB / Slice Timing Models
ILO
(propagation delay
REG
REG
after clock event
after clock event
REG
and
209
Related parts for XC5VLX50-1FFG324C
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![XC5VLX50-1FFG1153C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 1153FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-1FF1153I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 1153FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-1FF676I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-1FFG676I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-1FFG676C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 676FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-2FF676I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
FPGA Virtex®-5 Family 46080 Cells 65nm (CMOS) Technology 1V 676-Pin FCBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-3FFG676C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 676-FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-1FF324C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 324FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-2FF324C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 324FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-2FFG324C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 324FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-1FF1153C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 1153FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-1FF324I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 324FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-1FFG324I](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 324FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-2FFG676C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 676-FBGA
Manufacturer:
Xilinx Inc
Datasheet:
![XC5VLX50-2FF676C](/photos/6/73/67306/xilinx-_1136-fbga_tmb.jpg)
Part Number:
Description:
IC FPGA VIRTEX-5 50K 676FBGA
Manufacturer:
Xilinx Inc
Datasheet: