PEB3265F-V1.5 Infineon Technologies, PEB3265F-V1.5 Datasheet - Page 362

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PEB3265F-V1.5

Manufacturer Part Number
PEB3265F-V1.5
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of PEB3265F-V1.5

Lead Free Status / RoHS Status
Not Compliant
Preliminary
Parameter
DXA/B delay time
to high Z
TCA/B delay time on
TCA/B delay time off
1)
2)
7.7.2.2
Figure 93
Data Sheet
The PCLK frequency must be an integer multiple of the FSC frequency.
All delay times are made up by two components: an intrinsic time (min-time), caused by internal processings,
and a second component caused by external circuitry (
PCLK
FSC
DRA/B
DXA/B
TCA/B
t
50%
FSC_S
Double-Clocking Mode
PCM Interface Timing – Double-Clocking Mode
t
PCLK
t
FSC_H
t
DR_S
t
Symbol
t
t
t
DR_H
dDXhz
dTCon
dTCoff
t
PCLKh
min.
25
25
25
t
FSC
362
C
Load
typ.
,
t
t
dDX
dTCon
R
Limit Values
Pullup
> 1.5 k )
Electrical Characteristics
t
t
dDTCoff
dDXhz
50
t
0.4
t
(
C
max.
dTCon_min
dTCoff_min
R
Load
High Imp.
Pullup
C
[pF])
Load
[k ]
ezm22014.wmf
+
+
[pF]
2000-07-14
DuSLIC
Unit
ns
ns
ns

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