CYP15G0402DXB-BGI Cypress Semiconductor Corp, CYP15G0402DXB-BGI Datasheet - Page 2

• Manufacturer Part Number: CYP15G0402DXB-BGI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYP15G0402DXB-BGI

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02057 Rev. *G
As
CYP(V)15G0402DXB extends the HOTLink family to faster
data rates, while maintaining serial link compatibility (data,
command and BIST) with other HOTLink devices.The transmit
(TX) section of the CYP(V)15G0402DXB Quad HOTLink II
SERDES consists of four ten bit wide channels that accept a
preencoded character on every clock cycle. Transmission
characters are passed from the Transmit Input Register to a
Serializer. The serialized characters are output from a differ-
ential transmission line driver at a bit-rate of 10 or 20 times the
input reference clock.
The receive (RX) section of the CYP(V)15G0402DXB Quad
HOTLink II SERDES consists of four ten bit wide channels.
Each
PECL-compatible differential line receiver and, using a
completely integrated PLL Clock Synchronizer, recovers the
timing information necessary for data reconstruction. Each
recovered bit-stream is deserialized and framed into
characters. Recovered characters are then passed to the
receiver output register, along with a recovered character
clock.
CYP(V)15G0402DXB Transceiver Logic Block Diagram
Serializer
Phase
Buffer
a
Align
channel
TX
x10
second-generation
accepts
Deserializer
Framer
RX
x10
a
serial
HOTLink
Phase
Buffer
Serializer
Align
TX
x10
bit-stream
device,
Deserializer
Framer
from
RX
x10
the
a
The parallel input interface may be configured for numerous
forms of clocking to provide the high flexibility in system archi-
tecture.
Each transmit and receive channel contains an independent
BIST pattern generator and checker. This BIST hardware
allows at-speed testing of the interface data path.
HOTLink II devices are ideal for a variety of applications where
parallel interfaces can be replaced with high-speed,
point-to-point serial links. Some applications include intercon-
necting backplanes on switches, routers, servers and video
transmission systems.
The CYV15G0402DXB is verified by testing to be compliant to
all the pathological test patterns documented in SMPTE
EG34-1999, for both the SMPTE 259M and 292M signaling
rates. The tests ensure that the receiver recovers data with no
errors for the following patterns:
1. Repetitions of 20 ones and 20 zeros.
2. Single burst of 44 ones or 44 zeros.
3. Repetitions of 19 ones followed by 1 zero or 19 zeros fol-
Serializer
Phase
Buffer
Align
lowed by 1 one.
TX
x10
Deserializer
Framer
RX
x10
CYP15G0402DXB
CYV15G0402DXB
Serializer
Phase
Buffer
Align
TX
x10
Deserializer
Framer
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RX
x10
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