CYP15G0402DXB-BGI Cypress Semiconductor Corp, CYP15G0402DXB-BGI Datasheet - Page 14

• Manufacturer Part Number: CYP15G0402DXB-BGI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYP15G0402DXB-BGI

• Lead Free Status / RoHS Status: Not Compliant

Document #: 38-02057 Rev. *G
Analog Amplitude
While most signal monitors are based on fixed constants, the
analog amplitude level detection is adjustable. This allows
operation with highly attenuated signals, or in high-noise
environments. This adjustment is made through the SDASEL
signal, a three-level select
the detection of a valid signal at one of three levels, as listed
in Table 4. This control input affects the analog monitors for all
receive channels.
When a particular channel is configured for local loopback
(LPENx = HIGH), no line receivers are selected, and the LFIx
output for each channel reports only the receive VCO
frequency out-of-range and transition density status of the
associated transmit signal. When local loopback is active, the
Analog Signal Detect Monitors are disabled.
Table 4. Analog Amplitude Detect Valid Signal Levels
Transition Density
The Transition Detection logic checks for the absence of any
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received on
a channel, the Transition Detection logic for that channel will
assert LFIx. The LFIx output remains asserted until at least
one transition is detected in each of three adjacent received
characters.
Range Controls
The Clock/Data Recovery (CDR) circuit includes logic to
monitor the frequency of the Phase Locked Loop (PLL)
Voltage Controlled Oscillator (VCO) used to sample the
incoming data stream. This logic ensures that the VCO
operates at, or near the rate of the incoming data stream for
two primary cases:
To perform this function, the frequency of the VCO is periodi-
cally sampled and compared to the frequency of the REFCLK
input. If the VCO is running at a frequency beyond
+1500ppm
periodically forced to the correct frequency (as defined by
REFCLK, SPDSEL, and TXRATE) and then released in an
attempt to lock to the input data stream. The sampling and
relock period of the Range Control is calculated as follows:
RANGE CONTROL SAMPLING PERIOD = (REFCLK-
PERIOD) * (16000).
During the time that the Range Control forces the PLL VCO to
run at REFCLK*10 (or REFCLK*20 when TXRATE = HIGH)
Notes:
10. When a disabled receive channel is reenabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be
9.
• when the incoming data stream resumes after a time in
• when the incoming data stream is outside the acceptable
MID (Open) 280 mV p-p differential
SDASEL
which it has been “missing”
frequency range
The peak amplitudes listed in this table are for typical waveforms that have generally 3 – 4 transitions for every ten bits. In a worse case environment the signals
may have a sign-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
indeterminate for up to 2 ms.
HIGH
LOW
[8]
as defined by the reference clock frequency, it is
140 mV p-p differential
420 mV p-p differential
Typical Signal with Peak Amplitudes Above
[5]
input, which sets the trip point for
[9]
rate, the LFIx output will be asserted LOW. While the PLL is
attempting to re-lock to the incoming data stream, LFIx may be
either HIGH or LOW (depending on other factors such as
transition density and amplitude detection) and the recovered
byte clock (RXCLKx) may run at an incorrect rate (depending
on the quality or existence of the input serial data stream).
After a valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx should be
HIGH.
Receive Channel Enabled
The CYP(V)15G0402DXB contains four receive channels that
can be independently enabled and disabled. Each channel
can be enabled or disabled separately through the BOE[7:0]
inputs, as controlled by the RXLE latch-enable signal. When
RXLE is HIGH, the signals present on the BOE[7:0] inputs are
passed through the Receive Channel Enable Latch to control
the PLLs and logic of the associated receive channel. The
BOE[7:0] input associated with a specific receive channel is
listed in Table 2.
When RXLE is HIGH and BOE[x] is HIGH, the associated
receive channel is enabled to receive and recover a serial
stream. When RXLE is HIGH and BOE[x] is LOW, the
associated receive channel is disabled and powered down.
Any disabled channel will indicate an asserted LFIx output.
When RXLE returns LOW, the values present on the BOE[7:0]
inputs are latched in the Receive Channel Enable Latch, and
remain there until RXLE returns HIGH to open the latch
again.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate Clock/Data
Recovery (CDR) block within each receive channel. The clock
extraction function is performed by embedded phase-locked
loops (PLLs) that track the frequency of the transitions in the
incoming bit streams and align the phase of their internal
bit-rate clocks to the transitions in the selected serial data
streams.
Each CDR accepts a character-rate (bit-rate
half-character-rate (bit-rate
REFCLK input. This REFCLK input is used to
Regardless of the type of signal present, the CDR will attempt
to recover a data stream from it. If the frequency of the
recovered data stream is outside the limits of the range control
monitor, the CDR will switch to track REFCLK instead of the
data stream. Once the CDR output (RXCLKx) frequency
returns back close to REFCLK frequency, the CDR input will
be switched back to track the input data stream.
• ensure that the VCO (within the CDR) is operating at the
• to reduce PLL acquisition time
• and to limit unlocked frequency excursions of the VCO when
correct frequency.
there is no input data present at the selected Serial Line
Receiver.
[10]
÷
20) reference clock from the
CYP15G0402DXB
CYV15G0402DXB
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÷
10) or
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