WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 161
WG82577LM S LGWS
Manufacturer Part Number
WG82577LM S LGWS
Description
Manufacturer
Intel
Datasheet
1.WG82577LM_S_LGWS.pdf
(195 pages)
Specifications of WG82577LM S LGWS
Lead Free Status / RoHS Status
Supplier Unconfirmed
- Current page: 161 of 195
- Download datasheet (2Mb)
Intel
10.2.1.3.24 Shared Receive Address High 3 - SHRAH[3] (0x05454; RW)
10.2.1.3.25 Multiple Receive Queues Command register - MRQC (0x05818; RW)
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
15:0
17:16
18
29:19
30
31
1:0
15:2
21:16
31:22
Bits
Bits
RW
RO
RW
RO
RW
RW
RW
RW
RO
Type
Type
X
00b
0b
0x0
0b
0b
0x00b
0x0
0x0
0x0
Reset
Reset
Receive Address High (RAH). The upper 16 bits of the 48-bit Ethernet address n
(n=0…3).
Address Select (ASEL). Selects how the address is to be used. 00b means that it is
used to decode the destination MAC address.
VMDq output index (VIND). Defines the VMDq output index associated with a
receive packet that matches this MAC address (RAH and RAL).
Reserved. Reads as 0b. Ignored on write.
All Nodes Multicast Address valid (MAV). The all nodes multicast address
(33:33:00:00:00:01) is valid when this bit is set. Note that 0x33 is the first byte
on the wire.
Address valid (AV). When this bit is set the relevant address 3 is valid (compared
against the incoming packet).
Multiple Receive Queues Enable (MRxQueue). Enables support for multiple receive
queues and defines the mechanism that controls queue allocation. This field can
be modified only when receive to host is not enabled (RCTL.EN = 0).
00b = Multiple receive queues are disabled.
01b = Multiple receive queues as defined by Microsoft* RSS. The RSS field enable
bits define the header fields used by the hash function.
10b = VMDq enable, enables VMDq operation as defined in section receive.
queuing for virtual machine devices.
11b = Reserved.
Reserved.
RSS Field Enable. Each bit, when set, enables a specific field selection to be used
by the hash function. Several bits can be set at the same time.
Bit[16] = Enable TcpIPv4 hash function.
Bit[17] = Enable IPv4 hash function.
Bit[18] = Enable TcpIPv6 hash function.
Bit[19] = Enable IPv6Ex hash function.
Bit[20] = Enable IPv6 hash function.
Bit[21] = Reserved.
Reserved.
Description
Description
154
Related parts for WG82577LM S LGWS
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
Intel
Datasheet:
Part Number:
Description:
Microprocessor: Intel Celeron M Processor 320 and Ultra Low Voltage Intel Celeron M Processor at 600MHz
Manufacturer:
Intel Corporation
Part Number:
Description:
Intel 82550 Fast Ethernet Multifunction PCI/CardBus Controller
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 32 Mbit. Access speed 120 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 32 Mbit. Access speed 120 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 64 Mbit. Access speed 150 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel StrataFlash memory 32 Mbit. Access speed 100 ns
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
DA28F640J5A-1505 Volt Intel StrataFlash Memory
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
5 Volt Intel StrataFlash?? Memory
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
5 Volt Intel StrataFlash?? Memory
Manufacturer:
Intel Corporation
Part Number:
Description:
Intel 6300ESB I/O Controller Hub
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel 82801DB I/O Controller Hub (ICH4), Pb-Free SLI
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel 82801FB I/O Controller Hub (ICH6)
Manufacturer:
Intel Corporation
Datasheet:
Part Number:
Description:
Intel Strataflash Memory28F128J3 28F640J3 28F320J3
Manufacturer:
Intel Corporation
Datasheet: