WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 129

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Intel
10.2.1.1.2
®
5 Series Express Chipset MAC Programming Interface—82577 GbE PHY
Device Status Register - STATUS (0x00008; RO)
0
1
3:2
4
5
7:6
8
9
10
18:11
19
29:20
30
31
Bits
RO/V
RO/V
RO/V
RO/V
RO/V
RO/V
RO/V
RW/V/C
RW/V/C
RO
RO/V
RO
RO
RO/SN
Attribute
X
X
00b
X
1b
X
X
0b
1b
0x0
1b
0x0
0b
1b
Reset
Full Duplex (FD).
0b = Half duplex.
1b = Full duplex.
Reflects duplex setting of the MAC and/or link.
Link up (LU).
0b = No link established.
1b = Link established.
For this to be valid, the Set Link Up bit of the Device Control register
(CTRL.SU) must be set.
PHY Type Indication (PHYTYPE). Indicates that the 82577 attached to the
MAC and resulted mode of operation of the MAC/82577 Link buses.
00 = 82577.
01 =Reserved.
10 = Reserved.
11 = Reserved.
This field is loaded from the Shared Init control word in the NVM.
Transmission Paused (TXOFF). Indication of pause state of the transmit
function when symmetrical flow control is enabled.
PHY Power Up not (PHYPWR). RO bit that indicates the power state of the
82577.
0b = The 82577 is powered on in the active state.
1b = The 82577 is in the power down state.
The PHYPWR bit is valid only after PHY reset is asserted.
Note: The PHY power up indication reflects the status of the LANPHYPC
signaling to the 82577.
Link speed setting (SPEED). This bit reflects the speed setting of the MAC
and/or link.
00b = 10 Mb/s.
01b = 100 Mb/s.
10b = 1000 Mb/s.
11b = 1000 Mb/s.
Master Read Completions Blocked. This bit is set when the MAC receives a
completion with an error (EP = one or status!= successful).
It is cleared on PCI reset.
LAN Init Done. This bit is asserted following completion of the LAN
initialization from the Flash.
Software is expected to clear this field to make it usable for the next
initialization done event.
PHY Reset Asserted (PHYRA). This bit is R/W. Hardware sets this bit
following the assertion of a 82577 reset (either hardware or in-band). The
bit is cleared on writing 0b to it.
Reserved.
Master Enable Status. Cleared by the MAC when the Master Disable bit is
set and no master requests are pending by this function, otherwise this bit
is set. This bit indicates that no master requests are issued by this
function as long as the Master Disable bit is set.
Reserved. Reads as 0.
Reserved.
Clock Control ¼ (CLK_CNT_1_4). This bit is loaded from the NVM word
0x13 and indicates the MAC supports lowering its DMA clock to ¼ of its
value.
Description
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