WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 122

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

10.0
10.1
115
Intel
Interface
Register Byte Ordering
This section defines the structure of registers that contain fields carried over the
network. For example, L2, L3, L4 fields.
The following example is used to describe byte ordering over the wire (hex notation):
Last
...,06, 05, 04, 03, 02, 01, 00
where each byte is sent with the LS bit first. That is, the bit order over the wire for this
example is:
Last
..., 0000 0011, 0000 0010, 0000 0001, 0000 0000
The general rule for register ordering is to use host ordering (also called little endian).
Using the previous example, a 6-byte fields (such as a MAC address) is stored in a CSR
in the following manner:
The following listed exceptions use network ordering (also called big endian). Using the
previous example, a 16-bit field (such as EtherType) is stored in a CSR in the following
manner:
®
5 Series Express Chipset MAC Programming
Dword address (N)
Dword address (N + 4)
Dword aligned
or
Word aligned
DW address (N + 4)
82577 GbE PHY—Intel
First
Byte 3
0x03
...
Byte 3
...
0x00
®
5 Series Express Chipset MAC Programming Interface
Byte 2
0x02
...
Byte 2
...
0x01
First
Byte 1
0x01
0x05
Byte 1
0x00
...
Byte 0
0x00
0x04
Byte 0
0x01
...