WG82577LM S LGWS Intel, WG82577LM S LGWS Datasheet - Page 152

• Manufacturer Part Number: WG82577LM S LGWS
• Manufacturer: Intel

Specifications of WG82577LM S LGWS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

10.2.1.3.6
10.2.1.3.7
10.2.1.3.8
145
Flow Control Receive Threshold High - FCRTH (0x02168; RW)
This register contains the receive threshold used to determine when to send an XOFF
packet. It counts in units of bytes. This value must be at least eight bytes less than the
maximum number of bytes allocated to the Receive Packet Buffer (PBA, RXA), and the
lower three bits must be programmed to zero (8-byte granularity). Each time the
receive FIFO reaches the fullness indicated by RTH, hardware transmits a PAUSE frame
if the transmission of flow control frames is enabled.
Note that flow control reception/transmission are negotiated capabilities by the auto-
negotiation process. When the MAC is manually configured, flow control operation is
determined by the RFCE and TFCE bits of the Device Control register.
Receive Descriptor Base Address Low Queue - RDBAL (0x02800; RW)
This register contains the lower bits of the 64-bit descriptor base address. The lower
four bits are always ignored. The receive descriptor base address must point to a 16-
byte aligned block of data.
Receive Descriptor Base Address High Queue - RDBAH (0x02804; RW)
This register contains the upper 32 bits of the 64-bit descriptor base address.
2:0
15:3
31:16
3:0
31:4
31:0
Bits
Bit
Bit
RW
Type
RO
RW
RO
RO
RW
Type
Type
X
Reset
82577 GbE PHY—Intel
0x0
0x0
0x0
0x0
X
Reset
Reset
Receive Descriptor Base Address [63:32] (RDBAH).
Reserved. Must be written with 0.
Receive Threshold High (RTH). FIFO high water mark for flow control
transmission.
Reserved. Reads as 0b. Should be written to 0b for future compatibility.
Reserved. Ignored on writes. Returns 0b on reads.
Receive Descriptor Base Address Low (RDBAL).
®
5 Series Express Chipset MAC Programming Interface
Description
Description
Description