AM79C973BKC\W AMD (ADVANCED MICRO DEVICES), AM79C973BKC\W Datasheet - Page 50

• Manufacturer Part Number: AM79C973BKC\W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C973BKC\W

• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3/3.135V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 160
• Lead Free Status / RoHS Status: Not Compliant

Figure 15 shows a typical burst write access. The
Am79C973/Am79C975 controller arbitrates for the bus,
is granted access, and writes four 32-bit words
(DWords) to the system memory and then releases the
bus. In this example, the memory system extends the
data phase of the first access by one wait state. The fol-
lowing three data phases take one clock cycle each,
which is determined by the timing of TRDY. The exam-
ple assumes that EXTREQ (BCR18, bit 8) is set to 1,
therefore, REQ is not deasserted until the next to last
data phase is finished.
Target Initiated Termination
When the Am79C973/Am79C975 controller is a bus
master, the cycles it produces on the PCI bus may be
terminated by the target in one of three different ways:
50
DEVSEL
FRAME
TRDY
IRDY
C/BE
REQ
GNT
CLK
PAR
AD
1
DEVSEL is sampled
Figure 15. Burst Write Transfer (EXTREQ = 1)
2
ADDR
0111
P R E L I M I N A R Y
3
Am79C973/Am79C975
PAR
4
DATA
5
PAR
disconnect with data transfer, disconnect without data
transfer, and target abort.
Disconnect With Data Transfer
Figure 16 shows a disconnection in which one last data
transfer occurs after the target asserted STOP. STOP
is asserted on clock 4 to start the termination se-
quence. Data is still transferred during this cycle, since
both IRDY and TRDY are asserted. The Am79C973/
Am79C975 controller terminates the current transfer
with the deassertion of FRAME on clock 5 and of IRDY
one clock later. It finally releases the bus on clock 7.
The Am79C973/Am79C975 controller will again re-
quest the bus after two clock cycles, if it wants to trans-
fer more data. The starting address of the new transfer
will be the address of the next non-transferred data.
DATA
BE
6
DATA
PAR
7
DATA
PAR
8
PAR
9
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