82V2088BBG IDT, Integrated Device Technology Inc, 82V2088BBG Datasheet - Page 55

• Manufacturer Part Number: 82V2088BBG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V2088BBG

• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Compliant

OCTAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
Table-53 INTS1: Interrupt Status Register 1
4.2.9
Table-54 CNT0: Error Counter L-byte Register 0
Table-55 CNT1: Error Counter H-byte Register 1
DAC_OV_IS
CNT_OV_IS
CNT_H[7:0]
CNT_L[7:0]
TMOV_IS
JAOV_IS
JAUD_IS
Symbol
ERR_IS
Symbol
Symbol
EXZ_IS
CV_IS
COUNTER REGISTERS
(this register is reset and relevant interrupt request is cleared after a read) (R, Address = 17H,37H, 57H,77H,97H,B7H, D7H, F7H)
(R, Address = 19H,39H, 59H,79H,99H,B9H,D9H,F9H)
(R, Address = 18H,38H, 58H,78H,98H,B8H, D8H, F8H)
7-0
7-0
Bit
Bit
Bit
7
6
5
3
2
1
0
4
Default
Default
Default
00H
00H
0
0
0
0
0
0
0
0
This bit indicates the occurrence of the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event.
This bit indicates the occurrence of the Jitter Attenuator Overflow interrupt event.
This bit indicates the occurrence of the Counter Overflow interrupt event.
This register contains the upper eight bits of the 16-bit error counter. CNT_H[7] is the MSB.
= 0: no pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
= 1: the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
= 0: no JA overflow interrupt event occurred
= 1: A overflow interrupt event occurred
This bit indicates the occurrence of the Jitter Attenuator Underflow interrupt event.
= 0: no JA underflow interrupt event occurred
= 1: JA underflow interrupt event occurred
This bit indicates the occurrence of the interrupt event generated by the detected PRBS/QRSS logic error.
= 0: no PRBS/QRSS logic error interrupt event occurred
= 1: PRBS/QRSS logic error interrupt event occurred
This bit indicates the occurrence of the Excessive Zeros interrupt event.
= 0: no excessive zeros interrupt event occurred
= 1: EXZ interrupt event occurred
This bit indicates the occurrence of the Code Violation interrupt event.
= 0: no code violation interrupt event occurred
= 1: code violation interrupt event occurred
This bit indicates the occurrence of the One-Second Timer Expiration interrupt event.
= 0: no one-second timer expiration interrupt event occurred
= 1: one-second timer expiration interrupt event occurred
= 0: no counter overflow interrupt event occurred
= 1: counter overflow interrupt event occurred
This register contains the lower eight bits of the 16-bit error counter. CNT_L[0] is the LSB.
55
Description
Description
Description
TEMPERATURE RANGES
INDUSTRIAL