LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 459

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Chapter 17 Datasheet Revision History
SMSC LAN9311/LAN9311i
REVISION LEVEL & DATE
Rev. 1.7 (06-29-10)
Rev. 1.6 (08-19-09)
Rev. 1.5 (10-28-08)
Rev. 1.3 (07-03-08)
Table 3.5, “EEPROM Pins,”
on page 31
Table 3.5, “EEPROM Pins,”
on page 31
Section 14.2.8.4, "Virtual
PHY Identification LSB
Register (VPHY_ID_LSB),"
on page 252
14.4.2.4, "Port x PHY
Identification LSB Register
(PHY_ID_LSB_x)," on
page 294
Section 14.5.2.23, "Port x
MAC Transmit Configuration
Register
(MAC_TX_CFG_x)," on
page 346
Section 14.3.6, "Host MAC
MII Access Register
(HMAC_MII_ACC)," on
page 279
Table 6.1, “Switch Fabric
Flow Control Enable Logic,”
on page 59
Figure 15.2 nRST Reset Pin
Timing on page 445
All
Section 14.2.4.1, "EEPROM
Command Register
(E2P_CMD)," on page 198
Section 15.6, "Clock
Circuit," on page 454
All
Port x PHY Special
Control/Status Register
(PHY_SPECIAL_CONTROL
_STATUS_x) on page 308
Wake-Up Frame Detection
section of Host MAC
Chapter and MAC_CR
register description
SECTION/FIGURE/ENTRY
Table 17.1 Customer Revision History
and
DATASHEET
Section
459
Added note to EE_SDA and EE_SCL pin
descriptions stating “If I
pull-up is required when using an EEPROM and is
recommended if no EEPROM is attached.”
Added note to EEDO/EEPROM_TYPE pin
descriptions stating “When not using a Microwire
or I
recommended on this pin.”
Clarified default values using binary.
Added note to IFG Config field description:
Note:
Corrected MIIBZY bit type to read only, self-
clearing
Corrected rightmost column title to “TX FLOW
CONTROL ENABLE”
Updated figure shading.
Standard SMSC formatting applied.
Corrected CFG_LOADED bit type from “RO” to
“R/WC”
Changed max ESR value from 30 to 50 Ohms and
corrected typos in operating temerpature range.
Fixed various typos
Updated RESERVED bits 11:5 definition to
“RESERVED - Write as 0000010b, ignore on
read”, changed default to 0000010b, and made
field R/W.
Added note at end of WUFF section and to the
BCAST bit of the MAC_CR register stating:
When wake-up frame detection is enabled via the
WUEN bit of the HMAC_WUCSR register, a
broadcast wake-up frame will wake-up the device
despite the state of the Disable Broadcast Frames
(BCAST) bit in the HMAC_CR register.
2
C EEPROM, an external pull-down resistor is
IFG Config values less than 15 are
unsupported.
CORRECTION
2
C is selected, an external
Revision 1.7 (06-29-10)