LAN9311-NZW Standard Microsystems (SMSC), LAN9311-NZW Datasheet - Page 169

• Manufacturer Part Number: LAN9311-NZW
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LAN9311-NZW

• Number Of Primary Switch Ports: 2
• Internal Memory Buffer Size: 32
• Operating Supply Voltage (typ): 3.3V
• Fiber Support: No
• Integrated Led Drivers: Yes
• Phy/transceiver Interface: MII
• Power Supply Type: Analog
• Data Rate (typ): 10/100Mbps
• Vlan Support: Yes
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Pin Count: 128
• Mounting: Surface Mount
• Jtag Support: No
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temperature Classification: Commercial
• Data Rate: 100Mbps
• Lead Free Status / RoHS Status: Compliant

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
SMSC LAN9311/LAN9311i
14.2
ADDRESS
094h - 098h
OFFSET
05Ch
06Ch
07Ch
08Ch
050h
054h
058h
060h
064h
068h
070h
074h
078h
080h
084h
088h
090h
The System CSR’s are directly addressable memory mapped registers with a base address offset
range of 050h to 2DCh. These registers are addressable by the Host via the Host Bus Interface (HBI).
Table 14.1
reset to their default value on the assertion of a chip-level reset.
The System CSR’s can be divided into 9 sub-categories. Each of these sub-categories contains the
System CSR descriptions of the associated registers. The register descriptions are categorized as
follows:
System Control and Status Registers
Section 14.2.1, "Interrupts," on page 173
Section 14.2.2, "Host MAC & FIFO’s," on page 181
Section 14.2.3, "GPIO/LED," on page 193
Section 14.2.4, "EEPROM," on page 198
Section 14.2.5, "IEEE 1588," on page 202
Section 14.2.6, "Switch Fabric," on page 230
Section 14.2.7, "PHY Management Interface (PMI)," on page 244
Section 14.2.8, "Virtual PHY," on page 246
Section 14.2.9, "Miscellaneous," on page 260
lists the System CSR’s and their corresponding addresses in order. All system CSR’s are
RX_DP_CTRL
RX_FIFO_INF
TX_FIFO_INF
Table 14.1 System Control and Status Registers
BYTE_TEST
RESERVED
RESERVED
RESERVED
PMT_CTRL
SYMBOL
GPT_CFG
GPT_CNT
IRQ_CFG
FIFO_INT
HW_CFG
INT_STS
RX_CFG
TX_CFG
ID_REV
INT_EN
DATASHEET
169
Chip ID and Revision Register,
Interrupt Configuration Register,
Interrupt Status Register,
Interrupt Enable Register,
Reserved for Future Use
Byte Order Test Register,
FIFO Level Interrupts Register,
Receive Configuration Register,
Transmit Configuration Register,
Hardware Configuration Register,
RX Datapath Control Register,
Receive FIFO Information
Transmit FIFO Information Register,
Power Management Control Register,
Reserved for Future Use
General Purpose Timer Configuration Register,
Section 14.2.9.5
General Purpose Timer Count Register,
Reserved for Future Use
REGISTER NAME
Section 14.2.1.2
Section 14.2.9.2
Section 14.2.1.3
Register,Section 14.2.2.4
Section 14.2.2.3
Section 14.2.1.4
Section 14.2.9.1
Section 14.2.2.1
Section 14.2.1.1
Section 14.2.2.2
Section 14.2.9.3
Revision 1.7 (06-29-10)
Section 14.2.2.5
Section 14.2.9.4
Section 14.2.9.6