UJA1066TW/5V0,518 NXP Semiconductors, UJA1066TW/5V0,518 Datasheet - Page 14

• Manufacturer Part Number: UJA1066TW/5V0,518
• Manufacturer: NXP Semiconductors

Specifications of UJA1066TW/5V0,518

• Number Of Transceivers: 1
• Power Down Mode: Sleep/Standby
• Standard Supported: ISO 11898-2
• Operating Supply Voltage (min): 5.5V
• Operating Temperature (max): 125C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
UJA1066_2
Product data sheet
6.4.3 Watchdog time-out behavior
6.4.4 Watchdog OFF behavior
The watchdog window is defined to be between 50 % and 100 % of the nominal
programmed watchdog period. Any ‘too early’ or ‘too late’ watchdog access or incorrect
Mode register code access will result in an immediate system reset, when the SBC will
revert to Start-up mode.
When the SBC is in Standby, Sleep or Flash mode, the active watchdog operates in
Time-out mode. The watchdog has to be triggered within the programmed time frame (see
Figure
microcontroller from Standby and Sleep modes.
In Standby and Flash modes, the nominal periods can be changed with any SPI access to
the Mode register.
Any illegal watchdog trigger code results in an immediate system reset, when the SBC will
revert to Start-up mode.
In Standby and Sleep modes, the watchdog can be switched off entirely. For fail-safe
reasons this is only possible if the microcontroller has halted program execution. To
ensure that there is no continuing program execution, the V1 supply current is monitored
by the SBC while the watchdog is switched off.
When selecting the watchdog OFF code, the watchdog remains active until the
microcontroller supply current has dropped below the current monitoring threshold I
Once the supply current has dropped below this threshold, the watchdog stops at the end
of the watchdog period. The watchdog will remain active as long as the supply current
remains above the monitoring threshold.
Fig 5.
(with different duration if
5). Time-out mode can be used to generate cyclic wake-up events for the host
trigger
via SPI
trigger restarts period
Watchdog triggering using Time-out mode
possible
earliest
All information provided in this document is subject to legal disclaimers.
trigger
point
desired)
Rev. 03 — 17 March 2010
trigger range
period
High-speed CAN fail-safe system basis chip
trigger range
new period
possible
trigger
latest
point
time-out
UJA1066
© NXP B.V. 2010. All rights reserved.
time-out
mce627
thL(V1)
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